Kai Cheng

US Patent:

7058750, Jun 6, 2006

Filed:

May 10, 2000

Appl. No.:

09/569100

Inventors:

Linda J. Rankin - Beaverton OR, US
Paul R. Pierce - Portland OR, US
Gregory E. Dermer - Portland OR, US
Wen-Hann Wang - Portland OR, US
Kai Cheng - Portland OR, US
Richard H. Hofsheier - Banks OR, US
Nitin Y. Borkar - Beaverton OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 13/00

US Classification:

710317, 710310

Abstract:

A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.

US Patent:

7343442, Mar 11, 2008

Filed:

Jun 6, 2006

Appl. No.:

11/422542

Inventors:

Linda J. Rankin - Beaverton OR, US
Paul R. Pierce - Portland OR, US
Gregory E. Dermer - Portland OR, US
Wen-Hann Wang - Portland OR, US
Kai Cheng - Portland OR, US
Richard H. Hofsheier - Banks OR, US
Nitin Y. Borkar - Beaverton OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 13/00

US Classification:

710317, 710310

Abstract:

A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.

US Patent:

7444479, Oct 28, 2008

Filed:

Dec 28, 2005

Appl. No.:

11/321322

Inventors:

James W. Alexander - Aloha OR, US
Rajat Agarwal - Beaverton OR, US
Bruce A. Christenson - Forest Grove OR, US
Kai Cheng - Portland OR, US

International Classification:

G06F 12/16

US Classification:

711154, 711168

Abstract:

A memory controller uses a scheme to retire two entries from a replay queue due to a single non-error response. Advantageously, entries in a replay queue may be retired earlier than conventional systems, minimizing the size of the replay queue.

US Patent:

7603508, Oct 13, 2009

Filed:

Jan 14, 2008

Appl. No.:

12/013595

Inventors:

Linda J. Rankin - Beaverton OR, US
Paul R. Pierce - Portland OR, US
Gregory E. Dermer - Portland OR, US
Wen-Hann Wang - Portland OR, US
Kai Cheng - Portland OR, US
Richard H. Hofsheier - Banks OR, US
Nitin Y. Borkar - Beaverton OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 13/00

US Classification:

710317, 710310

Abstract:

A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.

US Patent:

7644347, Jan 5, 2010

Filed:

Sep 30, 2005

Appl. No.:

11/240111

Inventors:

James W. Alexander - Aloha OR, US
Suresh Chittor - Portland OR, US
Dennis W. Brzezinski - Sunnyvale CA, US
Kai Cheng - Portland OR, US
Henk Neefs - Palo Alto CA, US
Rajat Agarwal - Beaverton OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G11C 29/00

US Classification:

714799, 714758

Abstract:

Embodiments of the invention are generally directed to systems, methods, and apparatuses for mitigating silent data corruption using an error correction code having embedded signaling fault detection. In an embodiment, a memory controller includes an extended error correction code (ECC) and link signaling fault detection logic. The extended ECC includes embedded signaling fault detection. In one embodiment, the extended ECC augments the signaling fault detection capabilities of the signaling fault detection logic.

US Patent:

7734980, Jun 8, 2010

Filed:

Jun 24, 2005

Appl. No.:

11/165693

Inventors:

James W. Alexander - Aloha OR, US
Suresh Chittor - Beaverton OR, US
Dennis W. Brzezinski - Sunnyvale OR, US
Kai Cheng - Portland OR, US
Rajat Agarwal - Beaverton OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03M 13/00
G11C 29/00

US Classification:

714751, 714773, 714774

Abstract:

Embodiments of the invention are generally directed to systems, apparatuses, and methods for mitigating silent data corruption in a fully-buffered memory module architecture. In an embodiment, a memory controller includes a memory channel bit-lane error detector having an M-bit CRC and N-bit CRC, wherein N is less than M. The N-bit CRC is used if at least one bit-lane of the memory channel fails. In one embodiment, the memory controller selectively applies the strong error detection capability of an error correction code (ECC) in combination with the N-bit CRC to signal the need to resend faulty data, if at least one bit-channel has failed. Other embodiments are described and claimed.

US Patent:

7885914, Feb 8, 2011

Filed:

Dec 28, 2007

Appl. No.:

11/965955

Inventors:

James W. Alexander - Hillsboro OR, US
Son H. Lam - Puyallup WA, US
Devadatta V. Bodas - Federal Way WA, US
Krishna Kant - Portland OR, US
Kai Cheng - Portland OR, US
Ian M. Steiner - Hillsboro OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06N 5/02

US Classification:

706 46

Abstract:

Embodiments of the invention are generally directed to systems, methods, and apparatuses for rank coordination. In some embodiments, a host includes rank coordination logic. The rank coordination logic may include performance measurement logic to measure a performance of a memory channel and dwell period control logic to select a length of a dwell period based, at least in part, on the performance of the memory channel. Other embodiments are described and claimed.

US Patent:

7941618, May 10, 2011

Filed:

Aug 29, 2008

Appl. No.:

12/202088

Inventors:

James W. Alexander - Aloha OR, US
Rajat Agarwal - Beaverton OR, US
Bruce A. Christenson - Forest Grove OR, US
Kai Cheng - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 12/16

US Classification:

711154, 711167, 711E1204

Abstract:

A memory controller uses a scheme to retire two entries from a replay queue due to a single non-error response. Advantageously, entries in a replay queue may be retired earlier than conventional systems, minimizing the size of the replay queue.