Kang T Lee

US Patent:

6387456, May 14, 2002

Filed:

Sep 5, 2000

Appl. No.:

09/655123

Inventors:

William Patrick Allen - Portland CT
Nathan S. Jacobson - Westlake OH
Narottam P. Bansal - North Olmsted OH
Elizabeth J. Opila - Lakewood OH
James L. Smialek - Strongsville OH
Kang N. Lee - Westlake OH
Irene T. Spitsberg - Loveland OH
Hongyu Wang - Niskayuna NY
Peter Joel Meschter - Niskayuna NY
Krishan Lal Luthra - Schenectady NY

Assignee:

General Electric Company - NY
United Technologies Corporation - DE
The United States of America as represented by the Administrator of the National Aeronautics and Space Administration - Washington DC

International Classification:

C23C 406

US Classification:

427452, 427450, 427453

Abstract:

A barrier layer for a silicon containing substrate which inhibits the formation of gaseous species of silicon when exposed to a high temperature aqueous environment comprises a barium-strontium alumino silicate.

US Patent:

6410148, Jun 25, 2002

Filed:

Apr 15, 1999

Appl. No.:

09/292349

Inventors:

William Patrick Allen - Portland CT
Nathan S. Jacobson - Westlake OH
Elizabeth J. Opila - Lakewood OH
James L. Smialek - Strongsville OH
Kang N. Lee - Westlake OH
Irene T. Spitsberg - Loveland OH
Hongyu Wang - Niskayuna NY
Peter Joel Meschter - Niskayuna NY
Krishan Lal Luthra - Schenectady NY

Assignee:

General Electric Co. - New York
United Technologies Corp. - DE
The United States of America as represented by the Administrator of the National Aeronautics and Space Administration - Washington DC

International Classification:

B32B 900

US Classification:

428446, 428448, 428472, 4284722, 428701, 428702

Abstract:

A barrier layer for a silicon containing substrate which inhibits the formation of gaseous species of silicon when exposed to a high temperature aqueous environment comprises a barium-strontium alumino silicate.

US Patent:

20090164831, Jun 25, 2009

Filed:

Dec 19, 2007

Appl. No.:

11/959719

Inventors:

Hemanth K. Birru - Pennsburg PA, US
Kang W. Lee - Allentown PA, US

International Classification:

G06F 1/08

US Classification:

713601

Abstract:

An OTP and Reset Assert Counter and a method for protecting one-time programmable memory settings during read-out from an OTP memory block. The OTP memory block is set at ground and in a reset mode with a clock driven External Reset (RSTB) signal set at ground true active. A Delay Counter is programmed with a time delay to correspond with the time that is inherently needed by the OTP Memory block to complete a read-out process that begins with the External Reset (RSTB) signal being set to HIGH; and an input Clock signal is delayed by the Delay Counter for a duration of the time delay that begins with the External Reset (RSTB) signal being set to HIGH.

US Patent:

52908496, Mar 1, 1994

Filed:

Nov 6, 1992

Appl. No.:

7/972338

Inventors:

Kang I. Lee - Longmeadow MA

Assignee:

Monsanto Company - St Louis MO

International Classification:

C08F 830
C08F22014

US Classification:

524555

Abstract:

The ammonium salt of a polymer of styrene and maleic anhydride includes 0. 02 to 0. 20 weight fraction copolymerized C. sub. 1 -C. sub. 3 alkyl methacrylate to improve paper signing properties.

US Patent:

50681680, Nov 26, 1991

Filed:

Dec 20, 1990

Appl. No.:

7/630657

Inventors:

Kang I. Lee - Longmeadow MA

Assignee:

Monsanto Company - St. Louis MO

International Classification:

G03C 176
C08F21816

US Classification:

430270

Abstract:

Terpolymers of styrene, mono-iso-butyl maleate and mono-2-(n-butoxy)ethyl maleate wherein the ratio of styrene units to maleate units is in the range of about 1:1 to about 1. 6:1 and the ratio of mono-iso-butyl maleate units to mono-2-(n-butoxy)ethyl maleate is in the range of about 3:2 to about 1:3. The terpolymers are useful as alkali soluble binders for photoresist compositions.

US Patent:

61270474, Oct 3, 2000

Filed:

Feb 18, 1992

Appl. No.:

7/837619

Inventors:

Wayne L. Worrell - Penn Valley PA
Kang N. Lee - Philadelphia PA

Assignee:

The Trustees of the University of Pennsylvania - Philadelphia PA

International Classification:

B32B 1500

US Classification:

428615

Abstract:

High temperature alloys resistant to degradation and oxidation are provided. In accordance with preferred embodiments, alloys comprising from about 0. 1 to about 50 atomic percent silicon, from about 10 to about 80 atomic percent aluminum, and at least one metal selected from the group consisting of chromium, iridium, rhenium, palladium, platinum, rhodium, ruthenium, osmium, molybdenum, tungsten, niobium and tantalum are formed. Shaped bodies and structural members comprising such alloys are also described as are methods for their fabrication.

US Patent:

52370240, Aug 17, 1993

Filed:

Jun 11, 1992

Appl. No.:

7/897166

Inventors:

David E. Allberry - Enfield CT
Kang I. Lee - Longmeadow MA

Assignee:

Monsanto Company - St. Louis MO

International Classification:

C08F 206
C08F21814

US Classification:

526 75

Abstract:

A process which comprises reacting maleic anhydride and a primary or secondary C. sub. 1 -C. sub. 18 alcohol to form a maleic half ester, and then polymerizing the half ester and monoalkenyl aromatic monomer in ester solvent in the presence of a catalyst to form a solution of monoalkenyl aromatic monomer-maleic half ester copolymer having a weight average molecular weight of at least 110,000 Daltons. After formation of the copolymer, the reaction solution is neutralized to form a mixture of an alkaline salt solution of the copolymer and solvent and then the solvent is removed from the mixture.

US Patent:

57738670, Jun 30, 1998

Filed:

Mar 26, 1997

Appl. No.:

8/827352

Inventors:

Sailesh Chittipeddi - Emmaus PA
William Thomas Cochran - Clermont FL
Kang Woo Lee - Allentown PA

Assignee:

Lucent Technologies, Inc. - Murray Hill NJ

International Classification:

H01L 2978
G11C 1700

US Classification:

257390

Abstract:

A ROM (read only memory) is disclosed. For via-ROMs, an isolation transistor is used to isolate adjacent pairs of memory devices instead of the more conventional field oxide isolation. The gate of the isolation transistor is grounded, insuring that conduction does not take place. For a GASAD ROM, a field oxide isolation is used.