Kang Y Lee

US Patent:

7512028, Mar 31, 2009

Filed:

Apr 17, 2007

Appl. No.:

11/736208

Inventors:

James L. Archibald - Schnecksville PA, US
Kang W. Lee - Allentown PA, US
Edwin A. Muth - Bethlehem PA, US
Kreg D. Ulery - Bethlehem PA, US

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

G11C 17/18

US Classification:

3652257, 326 38, 326 39, 327525

Abstract:

In one embodiment, a integrated circuit (IC) configurable to have any one of a plurality of different feature sets, the IC including (a) one or more feature blocks adapted to be independently enabled or disabled, (b) a one-time-programmable (OTP) memory cell for each feature block, the OTP memory cell storing a value, and (c) a feature control module for each feature block, each feature control module connected between the corresponding OTP memory cell and the corresponding feature block, and adapted to enable or disable the corresponding feature block based on the value stored in the corresponding OTP memory cell. The OTP memory cells are programmed by a vendor to select the particular feature set for the IC which is to be available to a purchaser.

US Patent:

7626845, Dec 1, 2009

Filed:

Dec 13, 2006

Appl. No.:

11/610284

Inventors:

Kang W. Lee - Allentown PA, US
Joseph E. Simko - Whitehall PA, US
Yehuda Smooha - Allentown PA, US
Ying Zhu - Bethlehem PA, US

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

G11C 17/00

US Classification:

365 96, 365104, 36518916, 3652257, 326101, 326 47, 326 38

Abstract:

In one embodiment, the invention is an integrated circuit (IC) including an OTP memory and conditioning circuitry. The IC receives an externally-generated DC programming voltage signal that the conditioning circuitry transforms into a programming pulse signal for programming the OTP memory. The conditioning circuitry includes: (i) reset protection circuitry for holding the programming pulse signal low if the IC is powering up, (ii) an overvoltage protection circuit for substantially preventing the programming pulse voltage from exceeding predefined boundaries, and (iii) a conversion switch for controlling the programming pulse voltage. The programming pulse voltage is (i) substantially equivalent to the externally-generated DC voltage if an enable signal is on, and (ii) substantially equivalent to a reference voltage if the enable signal is off.

US Patent:

7852697, Dec 14, 2010

Filed:

Feb 17, 2009

Appl. No.:

12/372196

Inventors:

James L. Archibald - Schnecksville PA, US
Kang W. Lee - Allentown PA, US
Edwin A. Muth - Bethlehem PA, US
Kreg D. Ulery - Bethlehem PA, US

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

G11C 17/18

US Classification:

3652257, 326 38, 326 39, 327525

Abstract:

In one embodiment, a integrated circuit (IC) configurable to have any one of a plurality of different feature sets, the IC including (a) one or more feature blocks adapted to be independently enabled or disabled, (b) a one-time-programmable (OTP) memory cell for each feature block, the OTP memory cell storing a value, and (c) a feature control module for each feature block, each feature control module connected between the corresponding OTP memory cell and the corresponding feature block, and adapted to enable or disable the corresponding feature block based on the value stored in the corresponding OTP memory cell. The OTP memory cells are programmed by a vendor to select the particular feature set for the IC which is to be available to a purchaser.

US Patent:

57454019, Apr 28, 1998

Filed:

Feb 14, 1997

Appl. No.:

8/800346

Inventors:

Kang W. Lee - Allentown PA

Assignee:

Lucent Technologies Inc. - Murray Hill NJ

International Classification:

G11C 700

US Classification:

365104

Abstract:

Each column in the memory array of transistors of a programmable read only memory (ROM) can be programmed in either a conventional mode or an inverted mode. In the conventional mode, each transistor is either programmed (i. e. , connected to the corresponding bit line) or unprogrammed (i. e. , left unconnected to the corresponding bit line). In this way, the programming mode can be selected, independently for each column, to limit the maximum number of transistors that can be programmed in any given column to one half of the total number of transistors in the column. As such, the total capacitance along a bit line is reduced and the access time is therefore also reduced, resulting in a faster ROM. The information as to which columns are encoded using which programming modes is contained in a component of the ROM. That programming-mode information is accessed when reading data out of the memory array to determine whether or not to invert the data for the various columns.

US Patent:

54126061, May 2, 1995

Filed:

Mar 29, 1994

Appl. No.:

8/219059

Inventors:

Kang W. Lee - Allentown PA

Assignee:

AT&T Corp. - Murray Hill NJ

International Classification:

G11C 700

US Classification:

365203

Abstract:

An integrated circuit memory array includes column conductors that are precharged during a precharge period in order to reduce the effects of power supply voltage variations, a load resistor is connected between the column conductors and ground during a portion of the precharge period. In this manner, a voltage-divider is formed that provides a discharge path which prevents over-charging of the column conductors. An increase in power supply noise immunity is gained, thereby avoiding degradation of the worst-case memory access time that could otherwise occurs.

US Patent:

59333766, Aug 3, 1999

Filed:

Feb 28, 1997

Appl. No.:

8/808150

Inventors:

Kang Woo Lee - Allentown PA

Assignee:

Lucent Technologies Inc. - Murray Hill NJ

International Classification:

G11C 700

US Classification:

365200

Abstract:

An integrated circuit having a memory which includes an array of data storage cells is provided with a redundant array and a signal-directing circuit. A row or column signal for a defective cell, if present, as well as each successively higher row or column signal, is directed to sequentially higher address locations in the array to thereby avoid the defective cell address location. The last row or column signal is directed to the address location of the redundant array. A fuse is preferably associated with each row or column signal which may be selectively melted to direct the row or column signals. The array can be logically divided into subarrays each having an associated redundant array so that defects in each subarray can be accommodated.

US Patent:

57738670, Jun 30, 1998

Filed:

Mar 26, 1997

Appl. No.:

8/827352

Inventors:

Sailesh Chittipeddi - Emmaus PA
William Thomas Cochran - Clermont FL
Kang Woo Lee - Allentown PA

Assignee:

Lucent Technologies, Inc. - Murray Hill NJ

International Classification:

H01L 2978
G11C 1700

US Classification:

257390

Abstract:

A ROM (read only memory) is disclosed. For via-ROMs, an isolation transistor is used to isolate adjacent pairs of memory devices instead of the more conventional field oxide isolation. The gate of the isolation transistor is grounded, insuring that conduction does not take place. For a GASAD ROM, a field oxide isolation is used.