Karen Rose Baker

US Patent:

20230065622, Mar 2, 2023

Filed:

Sep 2, 2021

Appl. No.:

17/465633

Inventors:

- Waltham MA, US
Karen Kaneko Baker - Tucson AZ, US
Christopher Carbonneau - Marana AZ, US
Katherine J. Herrick - Tucson AZ, US
Teresa J. Clement - Tucson AZ, US
Jeffrey R. Laroche - Andover MA, US

International Classification:

H01L 23/427
H01L 25/065
H01L 23/00
H01L 25/00
H03F 3/24
H01Q 3/24

Abstract:

An Array Core Block for an AESA includes a stack of 2*M alternating N-channel RFIC and MMIC Power Amplifier wafers bonded together by a wafer-scale direct bond hybrid (DBH) interconnect process. This process forms both metal-to-metal and dielectric hydrogen bonds between bonding surfaces to seal the wafer stack. Each array core block includes an array of through substrate metal vias to distribute DC bias, LO and information signals. Each array core block also includes a cooling system including micro-channels formed on a backside of at least one of the chips in each bonded pair and through substrate via holes formed through the stack that operatively couple the micro-channels for all of the bonded pairs to receive and circulate a fluid through the micro-channels and through substrate via holes to cool the RFIC and MMIC Power Amplifier chips and to extract the heated fluid.