Karen L Moore

US Patent:

59337508, Aug 3, 1999

Filed:

Apr 3, 1998

Appl. No.:

9/054561

Inventors:

Syd R. Wilson - Phoenix AZ
Charles E. Weitzel - Mesa AZ
Mohit Bhatnagar - Chandler AZ
Karen E. Moore - Phoenix AZ
Thomas A. Wetteroth - Chandler AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 2158

US Classification:

438455

Abstract:

A method of fabricating a semiconductor device on thinned wide bandgap material including providing a support having a planar surface and a semiconductor substrate. Implanting a layer of ions in the substrate to create a layer of microbubbles defining a thin film having a planar surface and a remaining mass separated by the layer of implanted ions. Intimately contacting the planar surface of the thin film to the planar surface of the support and heating the support and substrate to separate the remaining mass from the thin film. A semiconductor device is formed on the thin film, and the support is thinned.

US Patent:

56416954, Jun 24, 1997

Filed:

Oct 2, 1995

Appl. No.:

8/538063

Inventors:

Karen E. Moore - Phoenix AZ
Charles E. Weitzel - Mesa AZ

Assignee:

Motorola - Schaumburg IL

International Classification:

H01L 21265
H01L 2120

US Classification:

438186

Abstract:

An implant mask (14) and an etch mask (16) are utilized in forming a silicon carbide JFET (10). A source opening (17) and a drain opening (18) are formed in the masks (14,16). The etch mask (16) is removed, and a source area (19) and a drain area 21 are implanted through the openings (17,18) and source and drain contact (23, 24) are formed. A protective layer (26) is used to form source and drain contacts (23,24). A gate contact (27) is utilized to ensure the gate (28) is self-aligned to the gate contact (27).

US Patent:

61804959, Jan 30, 2001

Filed:

Apr 3, 1998

Appl. No.:

9/054541

Inventors:

Syd R. Wilson - Phoenix AZ
Charles E. Weitzel - Mesa AZ
Mohit Bhatnagar - Chandler AZ
Karen E. Moore - Phoenix AZ
Thomas A. Wetteroth - Chandler AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 2130

US Classification:

438455

Abstract:

A silicon carbide transistor (10) is formed from a silicon carbide film (14) that is formed on a silicon carbide substrate bulk (37). A conductor pattern layer (25) is formed on the silicon carbide film (14) and the silicon carbide film (14) removed from the silicon carbide substrate bulk (37) and attached to a substrate (11) of a dissimilar semiconductor material.

US Patent:

20150357452, Dec 10, 2015

Filed:

Aug 17, 2015

Appl. No.:

14/827755

Inventors:

- Austin TX, US
Darrell G. Hill - Tempe AZ, US
Jenn Hwa Huang - Chandler AZ, US
Karen E. Moore - Phoenix AZ, US

International Classification:

H01L 29/778
H01L 29/205
H01L 29/20

Abstract:

A semiconductor device includes a semiconductor substrate configured to include a channel, first and second ohmic contacts supported by the semiconductor substrate, in ohmic contact with the semiconductor substrate, and spaced from one another for current flow between the first and second ohmic contacts through the channel, and first and second dielectric layers supported by the semiconductor substrate. At least one of the first and second ohmic contacts extends through respective openings in the first and second dielectric layers. The second dielectric layer is disposed between the first dielectric layer and a surface of the semiconductor substrate, and the second dielectric layer includes a wet etchable material having an etch selectivity to a dry etchant of the first dielectric layer.

US Patent:

20150295075, Oct 15, 2015

Filed:

Jun 26, 2015

Appl. No.:

14/752066

Inventors:

- Austin TX, US
Karen E. Moore - Phoenix AZ, US
Olin Hartin - Phoenix AZ, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 29/778
H01L 29/47
H01L 27/06
H01L 49/02
H01L 29/20
H01L 29/423

Abstract:

A low leakage current switch device () is provided which includes a GaN-on-Si substrate (-) covered by a passivation surface layer () in which a T-gate electrode with sidewall extensions () is formed and coated with a conformal passivation layer () so that the T-gate electrode sidewall extensions are spaced apart from the underlying passivation surface layer () by the conformal passivation layer ().