Karen K Moore

US Patent:

6630746, Oct 7, 2003

Filed:

May 9, 2000

Appl. No.:

09/566961

Inventors:

David P. Mancini - Fountain Hills AZ
Douglas J. Resnick - Phoenix AZ
Harland G. Tompkins - Chandler AZ
Karen E. Moore - Phoenix AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 2348

US Classification:

257797

Abstract:

An alignment mark ( ) is formed on the surface ( ) of a silicon carbide substrate ( ). The alignment mark ( ) is used to reflect a light signal ( ) to determine the proper position for the silicon carbide substrate ( ). The materials that are used to form the alignment mark ( ) can be used to form an alignment mark on any transparent or semi-transparent substrate and will maintain physical integrity through very high temperature processing steps.

US Patent:

7935620, May 3, 2011

Filed:

Dec 5, 2007

Appl. No.:

11/950820

Inventors:

Bruce M. Green - Gilbert AZ, US
Haldane S. Henry - Scottsdale AZ, US
Chun-Li Liu - Scottsdale AZ, US
Karen E. Moore - Phoenix AZ, US
Matthias Passlack - Chandler AZ, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 21/28

US Classification:

438570, 438572, 438575, 438580, 257E29041

Abstract:

Methods and apparatus are described for semiconductor devices. A method comprises providing a partially completed semiconductor device including a substrate, a semiconductor on the substrate, and a passivation layer on the semiconductor, and using a first mask, locally etching the passivation layer to expose a portion of the semiconductor, and without removing the first mask, forming a Schottky contact of a first material on the exposed portion of the semiconductor, then removing the first mask, and using a further mask, forming a step-gate conductor of a second material electrically coupled to the Schottky contact and overlying parts of the passivation layer adjacent to the Schottky contact. By minimizing the process steps between opening the Schottky contact window in the passivation layer and forming the Schottky contact material in this window, the gate leakage of a resulting field effect device having a Schottky gate may be substantially reduced.

US Patent:

8592878, Nov 26, 2013

Filed:

Mar 8, 2011

Appl. No.:

13/042948

Inventors:

Bruce M. Green - Gilbert AZ, US
Haldane S. Henry - Scottsdale AZ, US
Chun-Li Liu - Scottsdale AZ, US
Karen E. Moore - Phoenix AZ, US
Matthias Passlack - Chandler AZ, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 29/66

US Classification:

257280, 257 78, 257E29041

Abstract:

Embodiments include semiconductor devices with low leakage Schottky contacts. An embodiment is formed by providing a partially completed semiconductor device including a substrate, a semiconductor on the substrate, and a passivation layer on the semiconductor, and using a first mask, locally etching the passivation layer to expose a portion of the semiconductor. Without removing the first mask, a Schottky contact is formed of a first material on the exposed portion of the semiconductor, and the first mask is removed. Using a further mask, a step-gate conductor of a second material electrically coupled to the Schottky contact is formed overlying parts of the passivation layer adjacent to the Schottky contact. By minimizing the process steps between opening the Schottky contact window in the passivation layer and forming the Schottky contact material in this window, the gate leakage of a resulting field effect device having a Schottky gate may be substantially reduced.

US Patent:

20120156843, Jun 21, 2012

Filed:

Dec 17, 2010

Appl. No.:

12/971165

Inventors:

Bruce M. Green - Gilbert AZ, US
Darrell G. Hill - Tempe AZ, US
Karen E. Moore - Phoenix AZ, US

International Classification:

H01L 21/336

US Classification:

438261, 257E21441

Abstract:

A dielectric layer for a gallium nitride transistor is disclosed. In one example, the dielectric layer has a hydrogen content of less than or equal to 10% by atomic percentage. In one example, both a dielectric layer formed before a conductive electrode of the transistor and a dielectric layer formed after the conductive elective electrode have a hydrogen content of less than or equal to 10% by atomic percentage. In one example, the dielectric layer formed before the conductive electrode is formed by a LPCVD process and the dielectric layer formed after the conductive electrode is formed by a sputtering process.

US Patent:

20130277680, Oct 24, 2013

Filed:

Apr 23, 2012

Appl. No.:

13/453127

Inventors:

Bruce M. Green - Gilbert AZ, US
Karen E. Moore - Phoenix AZ, US
Olin Hartin - Phoenix AZ, US

International Classification:

H01L 29/20
H01L 21/336

US Classification:

257 76, 438285, 257E29089, 257E21409

Abstract:

A low leakage current switch device () is provided which includes a GaN-on-Si substrate (-) covered by a passivation surface layer () in which a T-gate electrode with sidewall extensions () is formed and coated with a conformal passivation layer () so that the T-gate electrode sidewall extensions are spaced apart from the underlying passivation surface layer () by the conformal passivation layer ().

US Patent:

20130341678, Dec 26, 2013

Filed:

Jun 26, 2012

Appl. No.:

13/533610

Inventors:

Bruce M. Green - Gilbert AZ, US
Darrell G. Hill - Tempe AZ, US
Jenn Hwa Huang - Chandler AZ, US
Karen E. Moore - Phoenix AZ, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 29/812
H01L 29/778
H01L 21/311

US Classification:

257192, 438703, 257E29317, 257E29246, 257E21253

Abstract:

A semiconductor device includes a semiconductor substrate configured to include a channel, a gate supported by the semiconductor substrate to control current flow through the channel, a first dielectric layer supported by the semiconductor substrate and including an opening in which the gate is disposed, and a second dielectric layer disposed between the first dielectric layer and a surface of the semiconductor substrate in a first area over the channel. The second dielectric layer is patterned such that the first dielectric layer is disposed on the surface of the semiconductor substrate in a second area over the channel.

US Patent:

20130341679, Dec 26, 2013

Filed:

Jun 26, 2012

Appl. No.:

13/533651

Inventors:

Bruce M. Green - Gilbert AZ, US
Darrell G. Hill - Tempe AZ, US
Jenn Hwa Huang - Chandler AZ, US
Karen E. Moore - Phoenix AZ, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 21/28
H01L 29/80

US Classification:

257192, 438660, 257E2931, 257E21158

Abstract:

A semiconductor device includes a semiconductor substrate configured to include a channel, first and second ohmic contacts supported by the semiconductor substrate, in ohmic contact with the semiconductor substrate, and spaced from one another for current flow between the first and second ohmic contacts through the channel, and first and second dielectric layers supported by the semiconductor substrate. At least one of the first and second ohmic contacts extends through respective openings in the first and second dielectric layers. The second dielectric layer is disposed between the first dielectric layer and a surface of the semiconductor substrate, and the second dielectric layer includes a wet etchable material having an etch selectivity to a dry etchant of the first dielectric layer.

US Patent:

59337508, Aug 3, 1999

Filed:

Apr 3, 1998

Appl. No.:

9/054561

Inventors:

Syd R. Wilson - Phoenix AZ
Charles E. Weitzel - Mesa AZ
Mohit Bhatnagar - Chandler AZ
Karen E. Moore - Phoenix AZ
Thomas A. Wetteroth - Chandler AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 2158

US Classification:

438455

Abstract:

A method of fabricating a semiconductor device on thinned wide bandgap material including providing a support having a planar surface and a semiconductor substrate. Implanting a layer of ions in the substrate to create a layer of microbubbles defining a thin film having a planar surface and a remaining mass separated by the layer of implanted ions. Intimately contacting the planar surface of the thin film to the planar surface of the support and heating the support and substrate to separate the remaining mass from the thin film. A semiconductor device is formed on the thin film, and the support is thinned.