Karthik M Sundaram

US Patent:

20200401524, Dec 24, 2020

Filed:

Aug 21, 2019

Appl. No.:

16/547557

Inventors:

- Suwon-si, KR
Karthik SUNDARAM - Austin TX, US

International Classification:

G06F 12/0864
G06F 12/1027
G06F 9/30

Abstract:

A high-frequency and low-power L1 cache and associated access technique. The method may include inspecting a virtual address of an L1 data cache load instruction, and indexing into a row and a column of a way predictor table using metadata and a virtual address associated with the load instruction. The method may include matching information stored at the row and the column of the way predictor table to a location of a cache line. The method may include predicting the location of the cache line within the L1 data cache based on the information match. A hierarchy of way predictor tables may be used, with higher level way predictor tables refreshing smaller lower level way predictor tables. The way predictor tables may be trained to make better predictions over time. Only selected circuit macros need to be enabled based on the predictions, thereby saving power.

US Patent:

20190278603, Sep 12, 2019

Filed:

May 23, 2019

Appl. No.:

16/421463

Inventors:

- Suwon-si, KR
Rama S. GOPAL - Austin TX, US
Karthik SUNDARAM - Austin TX, US

International Classification:

G06F 9/30
G06F 9/38
G06F 9/35
G06F 12/0875

Abstract:

A system and a method to cascade execution of instructions in a load-store unit (LSU) of a central processing unit (CPU) to reduce latency associated with the instructions. First data stored in a cache is read by the LSU in response a first memory load instruction of two immediately consecutive memory load instructions. Alignment, sign extension and/or endian operations are performed on the first data read from the cache in response to the first memory load instruction, and, in parallel, a memory-load address-forwarded result is selected based on a corrected alignment of the first data read in response to the first memory load instruction to provide a next address for a second of the two immediately consecutive memory load instructions. Second data stored in the cache is read by the LSU in response to the second memory load instruction based on the selected memory-load address-forwarded result.

US Patent:

20190235873, Aug 1, 2019

Filed:

Jun 26, 2018

Appl. No.:

16/019502

Inventors:

- Suwon-si, KR
Karthik SUNDARAM - Austin TX, US

International Classification:

G06F 9/38
G06F 9/30
G06F 12/0875

Abstract:

According to one general aspect, an apparatus may include a front end logic section comprising a main-branch target buffer (BTB). The apparatus may also include a micro-BTB separate from the main BTB, and configured to produce prediction information associated with a branching instruction and mark prediction information as verified when one or more conditions are satisfied. Wherein the front end logic section is configured to be, at least partially, powered down when the data stored by the micro-BTB that results in the prediction information is marked as previously verified.

US Patent:

20180267775, Sep 20, 2018

Filed:

Jun 2, 2017

Appl. No.:

15/612963

Inventors:

- Suwon-si, KR
Paul E. KITCHIN - Austin TX, US
Karthik SUNDARAM - Austin TX, US

International Classification:

G06F 7/485

Abstract:

According to one general aspect, a load unit may include a load circuit configured to load at least one piece of data from a memory. The load unit may include an alignment circuit configured to align the data to generate an aligned data. The load unit may also include a mathematical operation execution circuit configured to generate a resultant of a predetermined mathematical operation with the at least one piece of data as an operand. Wherein the load unit is configured to, if an active instruction is associated with the predetermined mathematical operation, bypass the alignment circuit and input the piece of data directly to the mathematical operation execution circuit.

US Patent:

20180267800, Sep 20, 2018

Filed:

Jun 6, 2017

Appl. No.:

15/615811

Inventors:

- Suwon-si, KR
Rama S. GOPAL - Austin TX, US
Karthik SUNDARAM - Austin TX, US

International Classification:

G06F 9/30
G06F 9/35
G06F 12/0875

Abstract:

A system and a method to cascade execution of instructions in a load-store unit (LSU) of a central processing unit (CPU) to reduce latency associated with the instructions. First data stored in a cache is read by the LSU in response a first memory load instruction of two immediately consecutive memory load instructions. Alignment, sign extension and/or endian operations are performed on the first data read from the cache in response to the first memory load instruction, and, in parallel, a memory-load address-forwarded result is selected based on a corrected alignment of the first data read in response to the first memory load instruction to provide a next address for a second of the two immediately consecutive memory load instructions. Second data stored in the cache is read by the LSU in response to the second memory load instruction based on the selected memory-load address-forwarded result.

US Patent:

20160019155, Jan 21, 2016

Filed:

Jun 3, 2015

Appl. No.:

14/730217

Inventors:

Arun RADHAKRISHNAN - Austin TX, US
Karthik SUNDARAM - Austin TX, US

International Classification:

G06F 12/08

Abstract:

According to one general aspect, a method may include monitoring a plurality of pre-fetch cache requests associated with a data stream. The method may also include evaluating an accuracy of the pre-fetch cache requests. The method may further include, based at least in part upon the accuracy of the pre-fetch cache requests, adjusting a maximum amount of data that is allowably pre-fetched in excess of a data stream's current actual demand for data.

US Patent:

20150199275, Jul 16, 2015

Filed:

Jul 7, 2014

Appl. No.:

14/325343

Inventors:

- Suwon-si, KR
Kevin LEPAK - Austin TX, US
Rama GOPAL - Austin TX, US
Murali CHINNAKONDA - Austin TX, US
Karthik SUNDARAM - Austin TX, US
Brian GRAYSON - Austin TX, US

International Classification:

G06F 12/08

Abstract:

According to one general aspect, an apparatus may include a cache pre-fetcher, and a pre-fetch scheduler. The cache pre-fetcher may be configured to predict, based at least in part upon a virtual address, data to be retrieved from a memory system. The pre-fetch scheduler may be configured to convert the virtual address of the data to a physical address of the data, and request the data from one of a plurality of levels of the memory system. The memory system may include a plurality of levels, each level of the memory system configured to store data.

US Patent:

20150199276, Jul 16, 2015

Filed:

Aug 4, 2014

Appl. No.:

14/451375

Inventors:

- Suwon-si, KR
Karthik SUNDARAM - Austin TX, US
Brian GRAYSON - Austin TX, US

International Classification:

G06F 12/08

Abstract:

According to one general aspect, a method may include receiving, by a pre-fetch unit, a demand to access data stored at a memory address. The method may include determining if a first portion of the memory address matches a prior defined region of memory. The method may further include determining if a second portion of the memory address matches a previously detected pre-fetched address portion. The method may also include, if the first portion of the memory address matches the prior defined region of memory, and the second portion of the memory address matches the previously detected pre-fetched address portion, confirming that a pre-fetch pattern is associated with the memory address.