Kathryn P O'Brien

US Patent:

7146607, Dec 5, 2006

Filed:

Sep 17, 2002

Appl. No.:

10/244564

Inventors:

Ravi Nair - Briarcliff Manor NY, US
John Kevin O'Brien - South Salem NY, US
Kathryn Mary O'Brien - South Salem NY, US
Peter Howland Oden - Ossining NY, US
Daniel Arthur Prener - Croton-on-Hudson NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/45

US Classification:

717151, 717153

Abstract:

A method (and system) of transparent dynamic optimization in a multiprocessing environment, includes monitoring execution of an application on a first processor with an execution monitor running on another processor of the system, and transparently optimizing one or more segments of the original application with a runtime optimizer executing on the another processor of the system.

US Patent:

8108843, Jan 31, 2012

Filed:

Sep 17, 2002

Appl. No.:

10/244682

Inventors:

Ravi Nair - Briarcliff Manor NY, US
John Kevin O'Brien - South Salem NY, US
Kathryn Mary O'Brien - South Salem NY, US
Peter Howland Oden - Ossining NY, US
Daniel Arthur Prener - Croton-on-Hudson NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/45

US Classification:

717139, 717138, 717151, 717152, 717153

Abstract:

A method (and system) for performing an emulation of an operation of a target computing system, includes interpreting a target instruction, recognizing an unused capacity of a host system when the host system is interpreting the instruction, and performing a translation of the instruction without increasing a time of interpreting the instruction.

US Patent:

8578351, Nov 5, 2013

Filed:

Dec 6, 2011

Appl. No.:

13/311858

Inventors:

Ravi Nair - Briarcliff Manor NY, US
John Kevin O'Brien - South Salem NY, US
Kathryn Mary O'Brien - South Salem NY, US
Peter Howland Oden - Ossining NY, US
Daniel Arthur Prener - Croton-on-Hudson NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/45
G06F 9/44

US Classification:

717139, 717114, 717148, 717158

Abstract:

In a host system, a method for using instruction scheduling to efficiently emulate the operation of a target computing system includes preparing, on the host system, an instruction sequence to interpret an instruction written for execution on the target computing system. An instruction scheduling on the instruction sequence is performed, to achieve an efficient instruction level parallelism, for the host system. A separate and independent instruction sequence is inserted, which, when executed simultaneously with the instruction sequence, performs to copy to a separate location a minimum instruction sequence necessary to execute an intent of an interpreted target instruction, the interpreted target instruction being a translation; and modifies the interpreter code such that a next interpretation of the target instruction results in execution of the translated version, thereby removing execution of interpreter overhead.

US Patent:

20040078186, Apr 22, 2004

Filed:

Sep 17, 2002

Appl. No.:

10/244434

Inventors:

Ravi Nair - Briarcliff Manor NY, US
John O'brien - South Salem NY, US
Kathryn O'brien - South Salem NY, US
Peter Oden - Ossining NY, US
Daniel Prener - Croton-on-Hudson NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F009/455

US Classification:

703/027000

Abstract:

A method (and system) of emulation in a multiprocessor system, includes performing an emulation in which a host multiprocessing system of the multiprocessor system supports a weak consistency model, and the target multiprocessing system of the multiprocessor system supports a strong consistency model.

US Patent:

58128115, Sep 22, 1998

Filed:

Feb 3, 1995

Appl. No.:

8/383331

Inventors:

Pradeep Kumar Dubey - White Plains NY
Charles Marshall Barton - Haworth NJ
Chiao-Mei Chuang - Cupertino CA
Linh Hue Lam - Yorktown Heights NY
John Kevin O'Brien - South Salem NY
Kathryn Mary O'Brien - South Salem NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 930
G06F 938

US Classification:

395392

Abstract:

A central processing unit (CPU) in a computer that permits speculative parallel execution of more than one instruction thread. The CPU uses Fork-Suspend instructions that are added to the instruction set of the CPU, and are inserted in a program prior to run-time to delineate potential future threads for parallel execution. The CPU has an instruction cache with one or more instruction cache ports, a bank of one or more program counters, a bank of one or more dispatchers, a thread management unit that handles inter-thread communications and discards future threads that violate dependencies, a set of architectural registers common to all threads, and a scheduler that schedules parallel execution of the instructions on one or more functional units in the CPU.