Kaveh Razazian

US Patent:

6628429, Sep 30, 2003

Filed:

Nov 10, 1999

Appl. No.:

09/438813

Inventors:

Kaveh Razazian - Aliso Viejo CA

Assignee:

Nortel Networks Limited - St. Laurent

International Classification:

H04N 132

US Classification:

358426, 358434, 358437, 358440, 358406, 379 9308

Abstract:

The present invention provides a system and method to effectively suppress idle fax signals. In one embodiment, the method includes detecting a fax indicator signal. The method further includes calculating a short term energy of the fax indicator signal. The method also includes calculating a short term energy of fax data subsequent to the fax indicator signal. In addition, the method includes discarding the fax data when the short term energy of the fax data fails to exceed the short term energy of the fax indicator signal.

US Patent:

7447200, Nov 4, 2008

Filed:

Aug 30, 2002

Appl. No.:

10/233171

Inventors:

Christina K. Chan - Northridge CA, US
Kaveh Razazian - Aliso Viejo CA, US
Farshad Meshkinpour - Los Angeles CA, US

Assignee:

Maxim Integrated Products, Inc. - Sunnyvale CA

International Classification:

H04L 12/56

US Classification:

370389, 370471, 710 62

Abstract:

In one embodiment, an adapter is configured for coupling to a power line to receive and propagate multiple types of information including voice and video. In general, the adapter comprises (i) a physical layer adapter including a plug for coupling to the power line and logic to support electrical and mechanical connections to the power line, and (ii) logic to process information contained in HomePlug frames received over the physical layer and to route the processed information to one of a plurality of peripheral devices including a telephone, a monitor and a video recorder.

US Patent:

8139614, Mar 20, 2012

Filed:

Jun 4, 2009

Appl. No.:

12/478701

Inventors:

Kaveh Razazian - Aliso Viejo CA, US
Maher Umari - Irvine CA, US
Victor V. Loginov - Irvine CA, US

Assignee:

Maxim Integrated Products, Inc. - Sunnyvale CA

International Classification:

H04J 3/06

US Classification:

370503, 375354

Abstract:

An embodiment is a method and apparatus to perform symbol synchronization. A correlation estimator computes a correlation of a sample vector representative of a narrowband signal. A synchronization detector detects symbol synchronization. Another embodiment is a method and apparatus to perform frame synchronization. A Fast Fourier Transform (FFT) processing unit computes a current FFT vector and an accumulated previous FFT vector. The current FFT vector and the accumulated previous FFT vector correspond to sample vectors associated with preamble symbols. A real and imaginary processing unit generates real and imaginary summations using the current FFT vector and the accumulated previous FFT vector. A mode processor generates mode flags representing operational modes using the real and imaginary summations.

US Patent:

8149967, Apr 3, 2012

Filed:

Jun 4, 2009

Appl. No.:

12/478689

Inventors:

Maher Umari - Irvine CA, US
Kaveh Razazian - Aliso Viejo CA, US
Victor V. Loginov - Irvine CA, US
Amir Hosein Kamalizad - Irvine CA, US

Assignee:

Maxim Integrated Products, Inc. - Sunnyvale CA

International Classification:

H04L 27/08
H04B 1/10
G08B 1/08

US Classification:

375345, 370350

Abstract:

An embodiment is a method and apparatus to process an input signal. An analog automatic gain control (AGC) processor controls an analog adjustable gain of the input signal using a feedback mechanism. The analog AGC processor generates a first signal. A processing circuit transforms the first signal into a second signal. A digital AGC processor controls a digital adjustable gain of the second signal using a feed-forward mechanism.

US Patent:

8165172, Apr 24, 2012

Filed:

Jun 4, 2009

Appl. No.:

12/478699

Inventors:

Kaveh Razazian - Aliso Viejo CA, US
Maher Umari - Irvine CA, US
Victor V. Loginov - Irvine CA, US

Assignee:

Maxim Integrated Products, Inc. - Sunnyvale CA

International Classification:

H04J 3/06

US Classification:

370503, 375354

Abstract:

An embodiment is a method and apparatus to perform symbol synchronization. A sign element obtains signs of samples in a sample vector. A correlation estimator computes a correlation of the sample vector. A synchronization detector detects symbol synchronization. Another embodiment is a method and apparatus to perform frame synchronization. A Fast Fourier Transform (FFT) processing unit computes a current FFT vector and an accumulated previous FFT vector. The current FFT vector and the accumulated previous FFT vector correspond to sample vectors associated with preamble symbols prior to symbol synchronization detection. A real and imaginary processing unit generates real and imaginary summations using the current FFT vector and the accumulated previous FFT vector. A mode processor generates mode flags representing operational modes using the real and imaginary summations.

US Patent:

8276025, Sep 25, 2012

Filed:

Jun 4, 2009

Appl. No.:

12/478679

Inventors:

Kaveh Razazian - Aliso Viejo CA, US
Amir Hosein Kamalizad - Irvine CA, US
Maher Umari - Irvine CA, US

Assignee:

Maxim Integrated Products, Inc. - Sunnyvale CA

International Classification:

G06F 11/00

US Classification:

714701

Abstract:

An embodiment is a method and apparatus to interleave data. A demultiplexer demultiplexes an input packet having N bits into L sub-packets on L branches. M flipping blocks flip M of the L sub-packets. M is smaller than L. L sub-interleavers interleave the (L-M) sub-packets and the M flipped sub-packets. A concatenator concatenates the interleaved sub-packets to form an output packet.

US Patent:

8284825, Oct 9, 2012

Filed:

Jun 4, 2009

Appl. No.:

12/478692

Inventors:

Amir Hosein Kamalizad - Irvine CA, US
Kaveh Razazian - Aliso Viejo CA, US
Maher Umari - Irvine CA, US

Assignee:

Maxim Integrated Products, Inc. - San Jose CA

International Classification:

H04B 17/00

US Classification:

375226, 375228, 375340, 375329, 375259, 370241

Abstract:

An embodiment is a method and apparatus to estimate channel quality. An absolute processor computes absolute real and imaginary values of real and imaginary parts, respectively, of output of a demodulator. A phase count unit generates first and second phase counts representing deviations from zero phase noise using the absolute real and imaginary values. An amplitude count unit generates first and second amplitude counts representing attenuation of a received signal using the absolute real and imaginary values. An integrator integrates the first and second phase counts and first and second amplitude counts into a signal quality indicator that represents a measure of quality of channel with respect to noise and fading.

US Patent:

8315152, Nov 20, 2012

Filed:

Jun 4, 2009

Appl. No.:

12/478618

Inventors:

Kaveh Razazian - Aliso Viejo CA, US
Maher Umari - Irvine CA, US
Amir Hosein Kamalizad - Irvine CA, US
Victor V. Loginov - Irvine CA, US
Michael V. Navid - Laguna Niguel CA, US

Assignee:

Maxim Integrated Products, Inc. - San Jose CA

International Classification:

H04J 11/00

US Classification:

370208, 370465, 725 79

Abstract:

According to one embodiment of the invention, an integrated circuit comprises an encoding module, a modulation module and a spectral shaped module. The encoding module includes an interleaver that adapted to operate in a plurality of modes including a first mode and a second mode. The interleaver performs repetitive encoding when placed in the second mode. The modulation module is adapted to compensate for attenuations that are to be realized during propagation of a transmitted signal over the power line. The spectral shaped module is adapted to compensate for amplitude distortion and further compensates for attenuations that will be realized during propagation of the transmitted signal over the power line.