Keith D Green

US Patent:

6642737, Nov 4, 2003

Filed:

Oct 15, 2001

Appl. No.:

09/978929

Inventors:

Paul Ehnis - Plano TX
Keith R. Green - Prosper TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G01R 3126

US Classification:

324769, 703 4, 703 14

Abstract:

A method of generating transistor scattering parameters employs a single circuit simulation with a self-correction scheme for the artificial DC voltage dropped across the 50-Ohm resistor representing transmission line impedance. A sub-circuit without 50-Ohm transmission line resistance is used to compute transistor bias current via a current-controlled voltage source to compensate for the DC voltage dropped across a 50-Ohm resistor contained in the network.

US Patent:

8170858, May 1, 2012

Filed:

Feb 27, 2009

Appl. No.:

12/394849

Inventors:

Borna Obradovic - McKinney TX, US
Keith Green - Prosper TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 17/50
G06G 7/62
G06G 7/48

US Classification:

703 14, 703 13, 703 4

Abstract:

Simulation of an electronic circuit including a model of a ferroelectric capacitor. The model of the ferroelectric capacitor includes a multi-domain ferroelectric capacitor, in which each of the domains is associated with a positive and a negative coercive voltage. A probability distribution function of positive and negative coercive voltages is defined, from which a weighting function of the distribution of domains having those coercive voltages is defined. The electrical behavior of the ferroelectric capacitor is evaluated by evaluating the polarization of each of the domains, as weighted by the weighting function. A time-dependent factor can be included in the polarization expression evaluated for each domain, to include the effect of relaxation. The effects of longer-term mechanisms, such as imprint, can be modeled by deriving a probability distribution function for the domains after an accelerated stress.

US Patent:

8380476, Feb 19, 2013

Filed:

Sep 29, 2009

Appl. No.:

12/568910

Inventors:

Borna Obradovic - McKinney TX, US
Keith R. Green - Prosper TX, US
Scott R. Summerfelt - Garland TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 17/50
G06G 7/62

US Classification:

703 13, 703 14

Abstract:

Simulation of an electronic circuit including a model of a ferroelectric capacitor. The model of the ferroelectric capacitor includes a multi-domain ferroelectric capacitor, in which each of the domains is associated with a positive and a negative coercive voltage. A probability distribution function of positive and negative coercive voltages is defined, from which a weighting function of the distribution of domains having those coercive voltages is defined. To create a model of a small ferroelectric capacitor, a Poisson probability distribution is assigned to each of an array of gridcells defining the probability distribution function of positive and negative coercive voltages, and a number of domains assigned to each gridcell is randomly selected according to that Poisson distribution and an expected number of domains in the modeled capacitor for that gridcell, based on the area of the modeled capacitor. The electrical behavior of the ferroelectric capacitor is evaluated by evaluating the superposed polarization of each of the randomly selected domains.

US Patent:

8429592, Apr 23, 2013

Filed:

Oct 20, 2011

Appl. No.:

13/277932

Inventors:

Yong Liu - Murphy TX, US
Keith R. Green - Prosper TX, US
Marie Denison - Plano TX, US
Yizhong Xie - Frisco TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 17/50

US Classification:

716136, 716115, 716132, 703 14

Abstract:

A process of operating a computer system to create a subcircuit model of an N/P configurable extended drain MOS transistor in which the subcircuit model includes an npn bipolar transistor and a pnp bipolar transistor which correspond to current paths through n-channel drift lanes and p-channel drift lanes during dual mode operation. A process of operating a computer system to simulate the behavior of an electronic circuit including a N/P configurable extended drain MOS transistor in which a subcircuit model of the N/P configurable extended drain MOS transistor includes an npn bipolar transistor and a pnp bipolar transistor which correspond to current paths through n-channel drift lanes and p-channel drift lanes during dual mode operation. A computer readable medium storing an electronic circuit simulation program that generates a simulation output of the behavior of an electronic circuit including a N/P configurable extended drain MOS transistor.

US Patent:

20100241413, Sep 23, 2010

Filed:

Mar 18, 2009

Appl. No.:

12/406423

Inventors:

Yong Liu - Murphy TX, US
Keith R. Green - Prosper TX, US
Sameer Pendharkar - Allen TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 17/50

US Classification:

703 14

Abstract:

A processor with a computer program product embodied thereon for modeling an LDMOS transistor having a drift region is provided. Characteristic behavior of a CMOS transistor with its body coupled to its source is generated, and characteristic behavior of a resistor is generated, where the resistor is coupled to the drain of the CMOS transistor. Then to account for impact ionization, an impact ionization current for electrons in the drift region an impact ionization current for holes in the drift region are calculated.

US Patent:

20110282639, Nov 17, 2011

Filed:

Jan 13, 2011

Appl. No.:

13/005892

Inventors:

Borna Obradovic - McKinney TX, US
Keith Green - Prosper TX, US

Assignee:

TEXAS INSTRUMENTS INCORPORATED - Dallas TX

International Classification:

G06F 17/50

US Classification:

703 14

Abstract:

A non-quasi-static model of the programming behavior of a floating-gate metal-oxide-semiconductor (MOS) transistor. This model is based on evaluation of a body current, for example determined as a function of voltages applied to the transistor from the circuit environment. The body current is used as an input to a non-quasi-static function on which the modeled gate injection current is based. In one example, the body current is applied to a representation of a series R-C circuit beginning from a time corresponding to the onset of avalanche breakdown, with the voltage across the capacitor serving as a control voltage of a voltage-controlled current source that drives the gate injection current. Integration of the gate injection current over the time interval of the programming pulse provides an estimate of the trapped charge at the floating gate.

US Patent:

20120112733, May 10, 2012

Filed:

Nov 9, 2010

Appl. No.:

12/942529

Inventors:

Anthony G. Antonacci - Allen TX, US
Keith R. Green - Prosper TX, US
Borna J. Obradovic - McKinney TX, US

Assignee:

TEXAS INSTRUMENTS INCORPORATED - Dallas TX

International Classification:

H03H 1/00

US Classification:

323368

Abstract:

A Hall effect device includes a Hall element and a voltage regulator. The Hall element has first and second bias terminals, or nodes. The Hall effect device maintains, or regulates, a voltage at a point within the Hall element between the first and second bias terminals at about a constant voltage level, while generating a Hall effect voltage. In particular embodiments, the Hall effect voltage is, thus, prevented from substantially varying with the temperature of the Hall element.

US Patent:

20220357369, Nov 10, 2022

Filed:

Jul 22, 2022

Appl. No.:

17/871873

Inventors:

- Dallas TX, US
Jo BITO - Dallas TX, US
Keith Ryan GREEN - Prosper TX, US

International Classification:

G01R 15/20
H01L 43/06
H01L 23/495
H01L 43/04

Abstract:

In one example, circuitry is formed in a semiconductor die. A magnetic concentrator is formed on a surface of the semiconductor die and over the circuitry. An isolation spacer is placed on a lead frame. The semiconductor die is placed on the isolation spacer, and the magnetic concentrator is aligned to overlap the lead frame. Electrical interconnects are formed between the semiconductor die and the lead frame.

Address:

16802 Park Hl Dr, Dallas, TX 75248

VIN:

1FTPW14V27KC24149

Make:

FORD

Model:

F-150

Year:

2007