Keith Quoc Lao from 815 Lone Star Dr, Cedar Park, TX 78613, age 66, Phone: (512)5294754

Name / Title

Company / Classification

Phones & Addresses

Keith Lao
Director

ETONG FINANCIAL, LLC
Investment Advisory Service

4516 Harvest Ln, Sachse, TX 75048
11532 Cedercliffe Dr, Austin, TX 78750

Keith Lao
Manager

SHINSEI LLC

8350 N Macarthur Blvd STE 190, Irving, TX 75063
11532 Cedarcliffe, Austin, TX 78750

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Location:

Austin, Texas Area

Industry:

Venture Capital & Private Equity

Languages:

English
Chinese
Vietnamese

Removable Transparent Membrane For A Pellicle
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US Patent:

8586267, Nov 19, 2013
Filed:

Sep 12, 2011
Appl. No.:

13/230572
Inventors:

Keith Lao - Austin TX, US
Assignee:

Samsung Austin Semiconductor, L.P. - Austin TX
Samsung Electronics Co., Ltd. - Suwon-Si
International Classification:

G03F 1/62
US Classification:

430 5
Abstract:

According to one embodiment, a pellicle includes first and second frame members that are selectively removable from one another. The second frame member has an annular shape similar to and is physically coupled to an outer periphery of a transparent membrane. The second frame member configured to be selectively coupled to the first frame member from a engaged position adjacent to the first frame member to a disengaged position in which the second frame member is separated from the first frame member.

Multi-Level Stack Having Multi-Level Contact And Method
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US Patent:

20130264717, Oct 10, 2013
Filed:

Apr 4, 2012
Appl. No.:

13/439087
Inventors:

Keith Lao - Austin TX, US
Assignee:

Samsung Austin Semiconductor - Austin TX
International Classification:

H01L 23/522
H01L 21/768
US Classification:

257774, 438637, 438631, 257E23145, 257E21577
Abstract:

A method for forming a multi-level stack having a multi-level contact is provided. The method includes forming a multi-level stack comprising a specified number, n, of conductive layers and at least n−1 insulating layers. A via formation layer is formed over the stack. A first via is etched in the via formation layer at a first edge of the stack. A first multi-level contact is formed in the first via. For a particular embodiment, a second via may be etched in the via formation layer at a second edge of the stack and a second multi-level contact may be formed in the second via.

Self Aligned Dual Inlaid Patterning And Etching
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US Patent:

6287960, Sep 11, 2001
Filed:

May 8, 2000
Appl. No.:

9/566500
Inventors:

Keith Q. Lao - Austin TX
Assignee:

Motorola, Inc. - Schaumburg IL
International Classification:

H01L 2124
H01L 2144
H01L 214763
US Classification:

438637
Abstract:

A semiconductor device fabrication method in which a conductive interconnect is formed over a semiconductor substrate. First and second dielectric films are formed over the interconnect. A first patterning layer is formed over the second dielectric. A via opening is then formed in the first patterning layer and a second patterning layer is formed over the first patterning layer. A trench opening is defined in the second patterning layer. A first portion of the second dielectric film exposed by the trench opening is removed to define a via pattern. A portion of the first patterning layer exposed by the second patterning layer is then removed to expose a second portion of the second dielectric film, which is then removed to define a trench portion of a dual inlaid opening in the second dielectric. A portion of the first dielectric film defined by the via pattern is then removed to expose the conductive region.

Multi-Level Stack Having Multi-Level Contact And Method
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US Patent:

20150357237, Dec 10, 2015
Filed:

Aug 17, 2015
Appl. No.:

14/828449
Inventors:

- Gyeonggi-do, KR
- Austin TX, US
Keith Lao - Austin TX, US
International Classification:

H01L 21/768
H01L 23/522
Abstract:

A method for forming a multi-level stack having a multi-level contact is provided. The method includes forming a multi-level stack comprising a specified number, n, of conductive layers and at least n-1 insulating layers. A via formation layer is formed over the stack. A first via is etched in the via formation layer at a first edge of the stack. A first multi-level contact is formed in the first via. For a particular embodiment, a second via may be etched in the via formation layer at a second edge of the stack and a second multi-level contact may be formed in the second via.

Forming Vias And Trenches For Self-Aligned Contacts In A Semiconductor Structure
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US Patent:

20140191409, Jul 10, 2014
Filed:

Jan 10, 2013
Appl. No.:

13/738629
Inventors:

- Gyeonggi-Do, KR
- Austin TX, US
Keith Quoc Lao - Austin TX, US
Assignee:

SAMSUNG AUSTIN SEMICONDUCTOR, L.P. - Austin TX
SAMSUNG ELECTRONICS CO., LTD. - Gyeonggi-Do
International Classification:

H01L 21/768
H01L 23/498
US Classification:

257774, 438667
Abstract:

A semiconductor structure is formed to include a non-conductive layer with at least one metal line, a first dielectric layer, a first stop layer, a second dielectric layer, a second stop layer, a third stop layer and a fourth stop layer. A first photoresist layer is formed over the upper stop layer to develop at least one via pattern. The structure is selectively etched to form the via pattern in the third stop layer through the fourth stop layer. The first photoresist layer is then removed. A second photoresist layer is formed over the upper stop layer to develop a plurality of trench patterns, each of the trench pattern comprising a via-trench portion in which the trench pattern is formed above the via pattern, and a trench portion that is remaining part of the trench pattern.