Keith E Roberts

US Patent:

6859813, Feb 22, 2005

Filed:

Dec 11, 2001

Appl. No.:

10/013568

Inventors:

Mark Steven Gorbics - Franklin Lakes NJ, US
Keith Michael Roberts - Chester NY, US

Assignee:

LeCroy Corporation - Chestnut Ridge NY

International Classification:

G06F017/17

US Classification:

708313, 708290

Abstract:

A decimation system and decimation circuit for decimating waveform data on an oscilloscope. The decimation circuit is implemented using sixteen parallel 16-to-1 multiplexers connected in parallel to a data bus which selectively captures samples based on control signals generated by a sample counting circuit. Decimation factor and phase values can be input to program the amount of decimation performed by the circuit. The decimation system provides even more flexibility in controlling the decimation and is formed by combining several of the decimation circuits with corresponding analog-to-digital converters and memory segments.

US Patent:

7124159, Oct 17, 2006

Filed:

Feb 18, 2005

Appl. No.:

11/061424

Inventors:

Mark Steven Gorbics - Franklin Lakes NJ, US
Keith Michael Roberts - Chester NY, US

Assignee:

LeCroy Corporation - Chestnut Ridge NY

International Classification:

G06F 17/17

US Classification:

708313, 708290

Abstract:

A decimation system and decimation circuit for decimating waveform data on an oscilloscope. The decimation circuit is implemented using sixteen parallel 16-to-1 multiplexers connected in parallel to a data bus which selectively captures samples based on control signals generated by a sample counting circuit. Decimation factor and phase values can be input to program the amount of decimation performed by the circuit. The decimation system provides even more flexibility in controlling the decimation and is formed by combining several of the decimation circuits with corresponding analog-to-digital converters and memory segments.

US Patent:

57038384, Dec 30, 1997

Filed:

Feb 16, 1996

Appl. No.:

8/602904

Inventors:

Mark S. Gorbics - Franklin Lakes NJ
Keith M. Roberts - Nyack NY
Richard L. Sumner - Pomona NY

Assignee:

LeCroy Corporation - Chestnut Ridge NY

International Classification:

G04F 800
H03K 513

US Classification:

368120

Abstract:

A Vernier delay line interpolator provides a precision level smaller than a clock period by delaying a periodic pulse signal in a delay line which has equally time-spaced taps and a total delay that is a harmonic H greater than 1 of the pulse period. The taps of the delay line are latched and decoded to derive the fraction of the pulse period that has passed. When the interpolator is combined with a coarse counter, misalignment between their outputs is prevented by having the coarse counter count both edges of the periodic pulse signal so as to provide redundant bits between the counter and the interpolator. If the redundant bits are not equal, the counter output is corrected before it is combined with the output of the interpolator.

US Patent:

58350500, Nov 10, 1998

Filed:

Oct 23, 1996

Appl. No.:

8/735928

Inventors:

Keith M. Roberts - Nyack NY

Assignee:

LeCroy Corporation - Chestnut Ridge NY

International Classification:

H03M 112

US Classification:

341172

Abstract:

A multi-range analog-to-digital converter for encoding rundown times into a single channel of pulse width encoded data which may be conveyed to a remote equipment room over a single inexpensive, low quality digital cable. An input charge pulse is divided into multiple charge pulses and rundown times of the divided charge pulses are combined and encoded into a single channel of encoded data. A digital value representation of the input charge pulse is derived from the most accurate rundown times selected from the single channel of encoded data.

US Patent:

58387544, Nov 17, 1998

Filed:

Mar 11, 1997

Appl. No.:

8/814835

Inventors:

Mark S. Gorbics - Franklin Lakes NJ
Keith M. Roberts - Nyack NY
Richard L. Sumner - Pomona NY

Assignee:

Lecroy Corporation - Chestnut Ridge NY

International Classification:

G06M 300

US Classification:

377 20

Abstract:

A Vernier delay line interpolator provides a precision level smaller than a clock period by delaying a periodic pulse signal in a delay line which has equally time-spaced taps and a total delay that is a harmonic H greater than 1 of the pulse period. The taps of the delay line are latched and decoded to derive the fraction of the pulse period that has passed. When the interpolator is combined with a coarse counter, misalignment between their outputs is prevented by having the coarse counter count both edges of the periodic pulse signal so as to provide redundant bits between the counter and the interpolator. If the redundant bits are not equal, the counter output is corrected before it is combined with the output of the interpolator.