Keith Alan Vanderlee

US Patent:

8085506, Dec 27, 2011

Filed:

Aug 27, 2007

Appl. No.:

11/845210

Inventors:

Kuen Chee Ee - Temecula CA, US
Christopher Gene Dunn - Austin TX, US
Keith Allan Vanderlee - Austin TX, US
Peter Sung Hahn - Wildomar CA, US

Assignee:

Magnecomp Corporation - Murrieta CA

International Classification:

G11B 5/48
G11B 21/16

US Classification:

3602458, 3602453, 3602459

Abstract:

A gimbal, a disk drive suspension that includes the gimbal, and a related method of manufacture, wherein the gimbal is configured to be coupled between a disk drive slider and a disk drive load beam. The gimbal includes a strut having a buss and a projection that is coupled to the buss. A combination of the projection and the buss define a gap.

US Patent:

8320083, Nov 27, 2012

Filed:

Dec 6, 2007

Appl. No.:

11/951619

Inventors:

Christopher Dunn - Austin TX, US
Keith A. Vanderlee - Austin TX, US

Assignee:

Magnecomp Corporation - Murrieta CA

International Classification:

G11B 21/16
G11B 5/48

US Classification:

3602459, 3602345, 3602458, 3602642

Abstract:

An electrical interconnect and a method of making an electrical interconnect in which a conductor has been substantially plated with a first protective metal shell, such as nickel, and a second outer metal shell, such as gold, before a covercoat has been applied. Such an electrical interconnect can be characterized as having an even-thickness outer shell on both its terminal pads and underneath the covercoat adjacent to the terminal pads, without overhangs or gaps near the bottom of the covercoat caused by surface etching during production.

US Patent:

57708916, Jun 23, 1998

Filed:

Sep 18, 1996

Appl. No.:

8/718120

Inventors:

Richard Francis Frankeny - Elein TX
Jerome Albert Frankeny - Taylor TX
Danny Edward Massey - Georgetown TX
Keith Allan Vanderlee - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2310
H01L 2332
H01L 23522

US Classification:

257727

Abstract:

A socket for attaching a flip chip die or ball grid array devices to a printed circuit board substrate having a pattern of solder covered lands, with resources for removing the flip chip die or ball grid array device, resources for directly aligning the solder balls of the flip chip die or ball grid array device to the printed circuit board, resources for using an interposer of dendrite coated vias or pads to electrically and physically connect the solder balls of the flip chip die or ball grid array devices to the solder deposits of the printed circuit board, resources for having the interposer reconfigure the wiring for testing or replacement purposes, resources for utilizing the flexibility and resilience of the interposer to improve dendrite connections, and resources for heat sinking the flip chip die or ball grid array device by direct thermal contact. The socket applies an evenly distributed force to connect the aligned flip chip die or ball grid array device solder ball pattern to the underlying printed circuit board solder deposit pattern through dendrite penetration of the solder using an interposer situated between and aligned to each such solder pattern.

US Patent:

56910410, Nov 25, 1997

Filed:

Sep 29, 1995

Appl. No.:

8/536880

Inventors:

Richard Francis Frankeny - Elgin TX
Jerome Albert Frankeny - Taylor TX
Danny Edward Massey - Georgetown TX
Keith Allan Vanderlee - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

B32B 300
H01R 458
H05K 500
H05K 716

US Classification:

428209

Abstract:

A socket for attaching a flip chip die or ball grid array devices to a printed circuit board substrate having a pattern of solder covered lands, with resources for removing the flip chip die or ball grid array device, resources for directly aligning the solder balls of the flip chip die or ball grid array device to the printed circuit board, resources for using an interposer of dendrite coated vias or pads to electrically and physically connect the solder balls of the flip chip die or ball grid array devices to the solder deposits of the printed circuit board, resources for having the interposer reconfigure the wiring for testing or replacement purposes, resources for utilizing the flexibility and resilience of the interposer to improve dendrite connections, and resources for heat sinking the flip chip die or ball grid array device by direct thermal contact. The socket applies an evenly distributed force to connect the aligned flip chip die or ball grid array device solder ball pattern to the underlying printed circuit board solder deposit pattern through dendrite penetration of the solder using an interposer situated between and aligned to each such solder pattern.

US Patent:

55092004, Apr 23, 1996

Filed:

Nov 21, 1994

Appl. No.:

8/342506

Inventors:

Jerome A. Frankeny - Taylor TX
Richard F. Frankeny - Austin TX
Ronald L. Imken - Round Rock TX
Keith A. Vanderlee - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01K 310

US Classification:

29852

Abstract:

Method and apparatus for fabricating fine pitch pattern multilayer printed circuit boards involving laminar stackable board layers providing power distribution, signal distribution and capacitive decoupling. In one respect, the invention relates to the fabrication of board layers by beginning with a metallic core, patterning the core, selectively enclosing the core in a dielectric, selectively depositing metal to form vias, plugs and signal lines, and forming dendrites with joining metallurgy on the vias and plugs to provide stackable connection from above or below the plane of the board layer. In another aspect, the invention is directed to the use of a sol-gel process to form a thin high dielectric constant crystalline film onto a metallic sheet followed with a deposition of a metallic layer onto the high dielectric constant film. The film serves as the dielectric of a capacitor layer which is thereafter in succession patterned, covered by a dielectric, and has selectively deposited a metallic layer for interconnecting the capacitor and forming vias. The ends of the vias are thereafter subject to dendritic growth and joining metallurgy to provide stackable interconnection capability.

US Patent:

47747609, Oct 4, 1988

Filed:

Oct 9, 1987

Appl. No.:

7/110070

Inventors:

Ronald J. Seaman - Austin TX
Keith A. Vanderlee - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H05K 334

US Classification:

29840

Abstract:

A solder preform and technique for making same is disclosed for use in a one time flux process for attaching electronic modules to printed circuit substrates via plated through holes or surface mount pads.

US Patent:

56002599, Feb 4, 1997

Filed:

Feb 9, 1996

Appl. No.:

8/599033

Inventors:

Bernd Bartyzel - Austin TX
Steven A. Duncan - Austin TX
Daniel A. Fields - Austin TX
Keith A. Vanderlee - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R 3102

US Classification:

324761

Abstract:

A multi-pin probe including a printed circuit board with multiple electrically conductive vias, multiple probes, each probe inserted into one of the electrically conductive vias, and a housing having multiple cavities inserted over the multiple probes, each cavity having a first and a second aperture around one of the probes, the first aperture being smaller than the second aperture. In addition, a method of manufacturing a multi-pin probe including the steps of manufacturing a printed circuit board with multiple electrically conductive vias, inserting multiple probes into the electrically conductive vias, and inserting a housing having multiple cavities over the multiple probes, each cavity having a first and a second aperture around one of the probes, the first aperture being smaller than the second aperture.

US Patent:

20210399653, Dec 23, 2021

Filed:

Sep 1, 2021

Appl. No.:

17/464248

Inventors:

- Murrieta CA, US
Peter Hahn - Bangkok, TH
David Glaess - Bangkok, TH
Keith A. Vanderlee - Midland TX, US

International Classification:

H02N 2/00
H01L 41/047
G11B 5/48
H02N 2/06
H02N 2/02

Abstract:

An electrical connection structure for connecting a piezoelectric element and an electrical circuit to each other with a conductive adhesive is described. The electrical connection structure includes an epoxy, a conductive component surrounded by the epoxy, and a trace feature implemented on top of the electrical connection structure.