Kelly D Fitzpatrick

US Patent:

7173783, Feb 6, 2007

Filed:

Sep 20, 2002

Appl. No.:

10/247929

Inventors:

John McEwen, legal representative - Porter TX, US
Bahjat Zafer - Sunnyvale CA, US
Pauline Bolte - San Jose CA, US
Ara Patapoutian - Westborough MA, US
Kelly Fitzpatrick - Sudbury MA, US
Steve Stupp - Los Altos CA, US

Assignee:

Maxtor Corporation - Longmont CO

International Classification:

G11B 5/09
G11B 27/36
H03D 1/00
H04L 27/06
H03M 13/03

US Classification:

360 46, 369 5922, 375341, 714796

Abstract:

A media noise optimized (MNO) detector for a read channel compensates for pattern dependent media noise, and compensates for nonlinearities from many sources such as residual MR nonlinearity, residual nonlinear transition shift, partial erasure, write-induced nonlinearity, and steady-state mis-equalization. The MNO detector is implemented by adjusting a conventional Viterbi detector branch metric so that the channel output value (ideal value) can be a nonlinear function of the state/branch bits, and the branch metric scaling factor is a function of the state/branch. For a given state/branch, the ideal value is the mean of analog-to-digital converter samples for the pattern corresponding to the state/branch, and the branch metric scaling factor is proportional to the noise variance for the pattern corresponding to that state/branch.

US Patent:

55640222, Oct 8, 1996

Filed:

Feb 9, 1994

Appl. No.:

8/193789

Inventors:

Goutam Debnath - Beaverton OR
Kelly J. Fitzpatrick - Beaverton OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 2704

US Classification:

395250

Abstract:

A method and apparatus for inserting clock buffers to reduce clock skew in a logic block in which the proper placement of the cells within the logic block is first determined. Given this cell placement and the location of the local clock lines, the placement of clock buffers within the logic block is determined such that the clock buffers are in close proximity to the local clock lines. Routing is then performed to connect the clock buffers to their corresponding clock trunks and the cells requiring clock signals to their corresponding clock buffers. The performance of the logic block is then evaluated. If the performance does not satisfy a predetermined minimum threshold then the cells are modified to satisfy the minimum threshold, or come closer to attaining it. The clock buffers are removed, and the proper placement of the new cells within the logic block is determined. Given this new cell placement a new set of clock buffers is placed and a new routing is created.

US Patent:

57420998, Apr 21, 1998

Filed:

Mar 19, 1997

Appl. No.:

8/821707

Inventors:

Goutam Debnath - Beaverton OR
Kelly Fitzpatrick - Beaverton OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 2348

US Classification:

257758

Abstract:

An integrated circuit and a process for manufacturing the same wherein the integrated circuit includes a substrate, a first insulative layer disposed on the substrate, and a first conductive layer disposed on the first insulative layer, the first conductive layer having a plurality of conductive channels arranged into horizontal tracks. The plurality of conductive channels are for providing two power sources V. sub. SS and V. sub. CC to cells (e. g. standard cells in control blocks) in the integrated circuit. A second insulative layer is disposed on the first conductive layer, and a second conductive layer is disposed on the second insulative layer, the second conductive layer arranged into a plurality of vertical tracks, each of the plurality of vertical tracks are broken into a plurality of segments. Each of the plurality of segments are for carrying one of the power sources, V. sub. SS and V. sub. CC to the cells in the integrated circuit, each of the plurality of segments coupled to a corresponding channel in the first conductive layer through first vias in the second insulative layer.

US Patent:

55863078, Dec 17, 1996

Filed:

Jun 30, 1993

Appl. No.:

8/086044

Inventors:

Keng L. Wong - Portland OR
Kelly J. Fitzpatrick - Beaverton OR
Jeffrey E. Smith - Aloha OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 112

US Classification:

395551

Abstract:

A clock distribution system and clock interrupt system for an integrated circuit device. Ignoring effects associated with the matched stages, the present invention includes a clock distribution and interrupt system for providing clock signals with less than 100 picoseconds of skew to various components of an integrated circuit device. The present invention utilizes several stages of drivers to evenly supply the distributed clock signals and each stage has RC matched input lines. The present invention advantageously locates the matched stages and clock drivers within the power supply ring of the integrated circuit located on the periphery of the microprocessor topology. This is done in order to better predict the topology surrounding these lines to match the capacitance of these lines. Further, this metal level offers a larger width dimension line (since as a top layer it may be thicker) having less resistance per unit area and also generally avoids spatial competition with other IC components and circuitry. The present invention additionally offers the capability of selectively powering down various components within the integrated device with a power management unit and enable network that is included as a component of the clock distribution system.

US Patent:

56969538, Dec 9, 1997

Filed:

Feb 8, 1996

Appl. No.:

8/597363

Inventors:

Keng L. Wong - Portland OR
Kelly J. Fitzpatrick - Beaverton OR
Jeffrey E. Smith - Aloha OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 110
G06F 132

US Classification:

395560

Abstract:

A clock distribution system and clock interrupt system for an integrated circuit device. Ignoring effects associated with the matched stages, the present invention includes a clock distribution and interrupt system for providing clock signals with less than 100 picoseconds of skew to various components of an integrated circuit device. The present invention utilizes several stages of drivers to evenly supply the distributed clock signals and each stage has RC matched input lines. The present invention advantageously locates the matched stages and clock drivers within the power supply ring of the integrated circuit located on the periphery of the microprocessor topology. This is done in order to better predict the topology surrounding these lines to match the capacitance of these lines. Further, this metal level offers a larger width dimension line (since as a top layer it may be thicker) having less resistance per unit area and also generally avoids spatial competition with other IC components and circuitry. The present invention additionally offers the capability of selectively powering down various components within the integrated device with a power management unit and enable network that is included as a component of the clock distribution system.