Kelly M Malone

US Patent:

7187081, Mar 6, 2007

Filed:

Oct 31, 2003

Appl. No.:

10/699238

Inventors:

Elbert E. Huang - Tarrytown NY, US
Kaushik A. Kumar - Beacon NY, US
Kelly Malone - Poughkeepsie NY, US
Dirk Pfeiffer - Dobbs Ferry NY, US
Muthumanickam Sankarapandian - Yorktown Heights NY, US
Christy S. Tyberg - Mahopac NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 29/40

US Classification:

257759, 257774, 438970

Abstract:

Interconnect structures having buried etch stop layers with low dielectric constants and methods relating to the generation of such buried etch stop layers are described herein. The inventive interconnect structure comprises a buried etch stop layer comprised of a polymeric material having a composition SiNCOH, where 0. 05≦v≦0. 8, 0≦w≦0. 9, 0. 05≦x≦0. 8, 0≦y≦0. 3, 0. 05≦z≦0. 8 for v+w+x+y+z=1; a via level interlayer dielectric that is directly below said buried etch stop layer; a line level interlayer dielectric that is directly above said buried etch stop layer; and conducting metal features that traverse through said via level dielectric, said line level dielectric, and said buried etch stop layer.

US Patent:

7396758, Jul 8, 2008

Filed:

Jan 3, 2007

Appl. No.:

11/619502

Inventors:

Elbert E. Huang - Tarrytown NY, US
Kaushik A. Kumar - Beacon NY, US
Kelly Malone - Poughkeepsie NY, US
Dirk Pfeiffer - Dobbs Ferry NY, US
Muthumanickam Sankarapandian - Yorktown Heights NY, US
Christy S. Tyberg - Mahopac NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/4763

US Classification:

438623, 257E21135

Abstract:

Interconnect structures having buried etch stop layers with low dielectric constants and methods relating to the generation of such buried etch stop layers are described herein. The inventive interconnect structure comprises a buried etch stop layer comprised of a polymeric material having a composition SiNCOH, where 0. 05≦v≦0. 8, 0≦w≦0. 9, 0. 05≦x≦0. 8, 0≦y≦0. 3, 0. 05≦z≦0. 08 for v+w+x+y+z=1; a via level interlayer dielectric that is directly below said buried etch stop layer; a line level interlayer dielectric that is directly above said buried etch stop layer; and conducting metal features that traverse through said via level dielectric, said line level dielectric, and said buried etch stop layer.

US Patent:

7879717, Feb 1, 2011

Filed:

Jun 17, 2008

Appl. No.:

12/140854

Inventors:

Elbert E. Huang - Tarrytown NY, US
Kaushik A. Kumar - Beacon NY, US
Kelly Malone - Poughkeepsie NY, US
Dirk Pfeiffer - Dobbs Ferry NY, US
Muthumanickam Sankarapandian - Yorktown Heights NY, US
Christy S. Tyberg - Mahopac NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/00

US Classification:

438637, 438970

Abstract:

Interconnect structures having buried etch stop layers with low dielectric constants and methods relating to the generation of such buried etch stop layers are described herein. The inventive interconnect structure comprises a buried etch stop layer comprised of a polymeric material having a composition SiNCOH, where 0. 05≦v≦0. 8, 0≦w≦0. 9, 0. 05≦x≦0. 8, 0≦y≦0. 3, 0. 05≦z≦0. 8 for v+w+x+y+z=1; a via level interlayer dielectric that is directly below said buried etch stop layer; a line level interlayer dielectric that is directly above said buried etch stop layer; and conducting metal features that traverse through said via level dielectric, said line level dielectric, and said buried etch stop layer.

US Patent:

8252226, Aug 28, 2012

Filed:

Sep 9, 2009

Appl. No.:

12/555947

Inventors:

Michael R. Reese - Houston TX, US
Kelly O. Malone - Houston TX, US

Assignee:

Varel International Ind., L.P. - Carrollton TX

International Classification:

C22C 1/05
C21D 9/00
C21D 9/22
C21D 7/04
B05D 1/12

US Classification:

419 18, 427367, 427350, 427445, 72 53

Abstract:

A high-energy treated cutter comprising a substrate having a top surface, an outer region, and an inner core and a wear resistant layer coupled to the top surface. The high-energy treatment alters the substrate's physical properties so that the inner core provides greater toughness and the outer region provides greater hardness, and greater abrasion resistance. The layer is protected prior to commencement of the treatment. In one embodiment, a cover is positioned to surround the layer and then the cutter undergoes treatment, wherein the cutter is subjected to impact forces with other cutters. In another embodiment, the cutter is positioned within a recess formed in a tray table, thereby providing protection to the layer. The cutter is secured in place via vacuum, glue, or weight. A spray nozzle applies shot material directed to the substrate of the cutter, thereby applying the impact forces to alter the substrate's properties.

US Patent:

8637412, Jan 28, 2014

Filed:

Aug 19, 2011

Appl. No.:

13/214157

Inventors:

Alfred Grill - White Plains NY, US
Kelly Malone - Newburgh NY, US
Son Van Nguyen - Schenectady NY, US
Vishnubhai Vitthalbhai Patel - Yorktown Heights NY, US
Hosadurga Shobha - Niskayuna NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/31
H01L 21/469

US Classification:

438778, 257288

Abstract:

A first PECVD process incorporating a silicon oxide precursor alone and then with an organo-silicon precursor with increasing flow while the flow of the silicon oxide precursor is reduced to zero provides a graded carbon adhesion layer whereby the content of C increases with layer thickness and a second PECVD process incorporating an organo-silicon precursor including an organic porogen provides a multiphase ultra-low k dielectric. The multiphase ultra-low k PECVD process uses high frequency radio frequency power just above plasma initiation in a PECVD chamber. An energy post treatment is also provided. A porous SiCOH dielectric material having a k less than 2. 7 and a modulus of elasticity greater than 7 GPa is formed.

US Patent:

20040130027, Jul 8, 2004

Filed:

Jan 7, 2003

Appl. No.:

10/338105

Inventors:

Stephen Gates - Ossining NY, US
Jeffrey Hedrick - Montvale NJ, US
Kelly Malone - Poughkeepsie NY, US
Satyanarayana Nitta - Poughquag NY, US
Christy Tyberg - Mahpoc NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L023/48
H01L023/52
H01L029/40

US Classification:

257/758000

Abstract:

A method and structure for forming an integrated circuit structure is disclosed that forms at least one first layer comprising logical and functional devices and forms at least one interconnection layer above the first layer. The interconnection layer is adapted to form electrical connections between the logical and functional devices. The interconnection layer is made by first forming a dielectric layer. The dielectric layer includes a first material and a second material, wherein the second material is less stable at manufacturing environmental conditions (e.g., the processing conditions discussed below) than the first material. The “second material” comprises a porogen and the “first material” comprises a matrix polymer. The invention then forms conductive features in the dielectric layer and removes (e.g., by heating) the second material from the dielectric layer to create air pockets in the interconnection layer where the second material was positioned.

US Patent:

20120285101, Nov 15, 2012

Filed:

Jul 27, 2012

Appl. No.:

13/560868

Inventors:

Michael R. Reese - Houston TX, US
Kelly O. Malone - Houston TX, US

Assignee:

Varel International Ind., L.P. - Carrollton TX

International Classification:

B24D 3/10
B24D 3/06
B24D 3/04

US Classification:

51309

Abstract:

A high-energy treated cutter comprising a substrate having a top surface, an outer region, and an inner core and a wear resistant layer coupled to the top surface. The high-energy treatment alters the substrate's physical properties so that the inner core provides greater toughness and the outer region provides greater hardness, and greater abrasion resistance. The layer is protected prior to commencement of the treatment. In one embodiment, a cover is positioned to surround the layer and then the cutter undergoes treatment, wherein the cutter is subjected to impact forces with other cutters. In another embodiment, the cutter is positioned within a recess formed in a tray table, thereby providing protection to the layer. The cutter is secured in place via vacuum, glue, or weight. A spray nozzle applies shot material directed to the substrate of the cutter, thereby applying the impact forces to alter the substrate's properties.