Kenneth William Key

age ~63

from Kailua Kona, HI

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Kenneth Key Phones & Addresses

Programmable Processing Engine For Efficiently Processing Transient Data
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US Patent:

6513108, Jan 28, 2003
Filed:

Jun 29, 1998
Appl. No.:

09/106478
Inventors:

Darren Kerr - Palo Alto CA
Kenneth Michael Key - Raleigh NC
Michael L. Wright - Raleigh NC
William E. Jennings - Cary NC
Assignee:

Cisco Technology, Inc. - San Jose CA
International Classification:

G06F 1516
US Classification:

712 19, 712 21
Abstract:

A programmable processing engine processes transient data within an intermediate network station of a computer network. The engine comprises an array of processing elements symmetrically arrayed as rows and columns, and embedded between input and output buffer units with a plurality of interfaces from the array to an external memory. The external memory stores non-transient data organized within data structures, such as forwarding and routing tables, for use in processing the transient data. Each processing element contains an instruction memory that allows programming of the array to process the transient data as processing element stages of baseline or extended pipelines operating in parallel.

Variable Stage Ratio Buffer Insertion For Noise Optimization In A Logic Network
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US Patent:

6990647, Jan 24, 2006
Filed:

Feb 19, 2002
Appl. No.:

10/078732
Inventors:

Kenneth Hing Key Tseng - Cupertino CA, US
Assignee:

Cadence Design Systems, Inc. - San Jose CA
International Classification:

G06F 17/50
US Classification:

716 8, 716 1, 716 6
Abstract:

A buffer for use in a logic circuit comprises input and output nodes. A first inverter having a first device size is coupled to the input node. A second inverter is coupled in series with the first inverter and with the output node. The second inverter having a second device size at least six times greater than the first device size. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. 37 CFR 1. 72(b).

Programmable Arrayed Processing Engine Architecture For A Network Switch
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US Patent:

7895412, Feb 22, 2011
Filed:

Jun 27, 2002
Appl. No.:

10/184564
Inventors:

Darren Kerr - Palo Alto CA, US
Kenneth Michael Key - Raleigh NC, US
Michael L. Wright - Raleigh NC, US
William E. Jennings - Cary NC, US
Assignee:

Cisco Tehnology, Inc. - San Jose CA
International Classification:

G06F 15/80
US Classification:

712 14, 712 22
Abstract:

A programmable processing engine processes transient data within an intermediate network station of a computer network. The engine comprises an array of processing elements symmetrically arrayed as rows and columns, and embedded between input and output buffer units with a plurality of interfaces from the array to an external memory. The external memory stores non-transient data organized within data structures, such as forwarding and routing tables, for use in processing the transient data. Each processing element contains an instruction memory that allows programming of the array to process the transient data as processing element stages of baseline or extended pipelines operating in parallel.