Kenneth Wayne Newton

US Patent:

6455411, Sep 24, 2002

Filed:

Sep 6, 2001

Appl. No.:

09/947966

Inventors:

Ping Jiang - Plano TX
Francis G. Celii - Dallas TX
Kenneth J. Newton - McKinney TX
Hiromi Sakima - Richardson TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21308

US Classification:

438624, 438638, 438706, 438790

Abstract:

A dual damascene process for low-k or ultra low-k dielectric such as organo-silicate glass (OSG). After the via ( ) etch, a trench ( ) is etched in the OSG layer ( ) using a less-polymerizing fluorocarbon added to an etch chemistry comprising a fluorocarbon and low N /Ar ratio. The low N /Ar ratio controls ridge formation during the trench etch. The combination of a less-polymerizing fluorocarbon with a higher-polymerizing fluorocarbon achieves a high etch rate and defect-free conditions.

US Patent:

6720247, Apr 13, 2004

Filed:

Oct 25, 2001

Appl. No.:

10/001327

Inventors:

Brian K. Kirkpatrick - Allen TX
Michael Morrison - Tempe AZ
Andrew J. McKerrow - Dallas TX
Kenneth J. Newton - McKinney TX
Dirk N. Anderson - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01J 214763

US Classification:

438622, 438618, 438692

Abstract:

A low-k dielectric layer ( ) is treated with a dry H plasma pretreatment to improve patterning. Resist poisoning occurs due to an interaction between low-k films ( ), such as OSG, and DUV resist ( ). The H plasma pre-treatment is performed to either pretreat a low-k dielectric ( ) before forming the pattern ( ) or during a rework of the pattern ( ).

US Patent:

6723636, Apr 20, 2004

Filed:

May 28, 2003

Appl. No.:

10/447513

Inventors:

Noel M. Russell - Plano TX
Kenneth Joseph Newton - McKinney TX
Changming Jin - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 214763

US Classification:

438634, 438637, 438638

Abstract:

According to one embodiment of the invention, a method for forming multiple layers of a semiconductor device is provided. The method includes defining a via through a dielectric layer that overlies a first layer. The first layer comprises a conductive portion that at least partly underlies the via. The method also includes overfilling the via with a dielectric material to form a second layer that overlies the dielectric layer. The method also includes forming a trench that is connected to the via by etching through the second layer and the dielectric material in the via.

US Patent:

6774031, Aug 10, 2004

Filed:

Dec 8, 2003

Appl. No.:

10/732665

Inventors:

Abbas Ali - Plano TX
Kenneth J. Newton - McKinney TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 214763

US Classification:

438638, 438624, 438640, 438673, 438687, 438701, 438636

Abstract:

A first dielectric layer ( ) and a second dielectric layer ( ) are formed over an etch stop layer ( ). A hardmask layer ( ) is formed over the second dielectric layer and a via ( ) is formed in the first dielectric layer ( ) and the second dielectric layer ( ). A trench ( ) is formed mostly in the second dielectric layer ( ) by fully or partially removing BARC from the via ( ) are partially etching the trench ( ) and prior to completion of the trench etch process.

US Patent:

6797633, Sep 28, 2004

Filed:

Sep 28, 2001

Appl. No.:

09/966605

Inventors:

Ping Jiang - Plano TX
Robert Kraft - Plano TX
Kenneth J. Newton - McKinney TX
Daty M. Rogers - Richardson TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21302

US Classification:

438706, 438710, 438712, 438720

Abstract:

After via etch, a low-k dielectric layer ( ) is treated with an in-situ O plasma. Resist poisoning is caused by a N source that causes an interaction between low-k films ( ), such as OSG, and DUV resist ( ). The in-situ plasma treatment immediately removes the source of poisoning to reduce or eliminate poisoning at trench patterning.

US Patent:

6861348, Mar 1, 2005

Filed:

Oct 18, 2001

Appl. No.:

09/982654

Inventors:

Brian K. Kirkpatrick - Allen TX, US
Michael Morrison - Tempe AZ, US
Andrew J. McKerrow - Dallas TX, US
Kenneth J. Newton - McKinney TX, US
Dirk N. Anderson - Plano TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L021/4763

US Classification:

438626, 438633, 438638, 438672

Abstract:

A low-k dielectric layer () is treated with a dry-wet (D-W) or dry-wet-dry (D-W-D) process to improve patterning Resist poisoning occurs due to an interaction between low-k films (), such as OSG, and DUV resist (). The D-W or D-W-D treatment is performed to either pretreat a low-k dielectric () before forming the pattern () or during a rework of the pattern ().

US Patent:

6872665, Mar 29, 2005

Filed:

Jun 22, 2000

Appl. No.:

09/599718

Inventors:

Francis G. Celii - Dallas TX, US
Guoqiang Xing - Plano TX, US
Andrew McKerrow - Dallas TX, US
Andrew Ralston - Richardson TX, US
Zhicheng Tang - Plano TX, US
Kenneth J. Newton - McKinney TX, US
Robert Kraft - Plano TX, US
Jeff West - San Antonio TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L021/20

US Classification:

438700, 438724, 438722, 438725, 438745, 438757

Abstract:

A dual damascene process flow for forming interconnect lines and vias in which at least part of the via () is etched prior to the trench etch. A low-k material such as a thermoset organic polymer is used for the ILD () and IMD (). After the at least partial via etch, a BARC () is deposited over the structure including in the via (). Then, the trench () is patterned and etched. Although at least some of the BARC () material is removed during the trench etch, the bottom of the via () is protected.

US Patent:

7727885, Jun 1, 2010

Filed:

Aug 29, 2006

Appl. No.:

11/511698

Inventors:

Phillip Daniel Matz - Murphy TX, US
Sopa Chevacharoenkul - Richardson TX, US
Basab Chatterjee - Allen TX, US
Anand Reddy - Dallas TX, US
Kenneth Joseph Newton - McKinney TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/44

US Classification:

438634, 438653, 438799, 438678, 257E21586, 257E21579, 257E21584

Abstract:

A semiconductor device is fabricated while mitigating conductive void formation in metallization layers. A substrate is provided. A first dielectric layer is formed over the substrate. A conductive trench is formed within the first dielectric layer. An etch stop layer is formed over the first dielectric layer. A second dielectric layer is formed over/on the etch stop layer. A resist mask is formed over the device and via openings are etched in the second dielectric layer. The resist mask is removed by an ash process. A clean process is performed that mitigates/reduces surface charge on exposed portions of the etch stop layer. Additional surface charge reduction techniques are employed. The via openings are filled with a conductive material and a planarization process is performed to remove excess fill material.

Address:

1002 Bonanza Dr, Arlington, TX 76001

Phone:

(817)4738368

VIN:

5NMSH13E27H007329

Make:

HYUNDAI

Model:

SANTA FE

Year:

2007