Kenneth S Richardson

US Patent:

6614269, Sep 2, 2003

Filed:

Aug 13, 2002

Appl. No.:

10/217785

Inventors:

Kenneth G. Richardson - Erie CO
Peter Windler - Fort Collins CO

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H03D 100

US Classification:

327 58, 327 50

Abstract:

A polyphase amplitude detector for detecting the amplitude of a polyphase signal. The polyphase amplitude detector includes means for generating differential pair signals. The differential pair signals are buffered and amplified and then AC coupled to the amplitude detector. The amplitude detector detects the amplitude of each phase of the polyphase signal and generates output signals which are used to control the amplitude of the polyphase signal.

US Patent:

6617889, Sep 9, 2003

Filed:

May 29, 2002

Appl. No.:

10/156963

Inventors:

Kenneth G. Richardson - Erie CO

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H03K 5153

US Classification:

327 77, 327 82, 327 89

Abstract:

A signal amplitude comparator which includes a first differential input circuit that is biased, is configured to receive an input voltage and is configured to generate a first output current that is a non-linear function of the input voltage, a second differential input circuit which is biased similarly to the first differential input circuit, is configured to receive a reference input voltage and is configured to generate a second output current that generally tracks process, temperature and supply variation, and a comparator which is connected to the first differential input circuit and the second differential input circuit and is configured to receive the first output current from the first differential input circuit and the second output current from the second differential input circuit. The comparator is configured to compare the first and second output currents and generate an output which indicates whether the input voltage exceeds a pre-determined threshold value.

US Patent:

6784745, Aug 31, 2004

Filed:

Jan 31, 2003

Appl. No.:

10/357030

Inventors:

Kenneth G. Richardson - Erie CO

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H03F 304

US Classification:

330288, 330304, 323315

Abstract:

A current amplifier has a variable resistor or capacitor to provide a high frequency boost. Additionally, additional transistors may be switched in and out of the circuit to provide different gains at lower frequency. The combination of variable resistors or capacitors and the switchable transistors provides control over the low frequency gain of the amplifier and the transition region from low gain to higher gain.

US Patent:

6864748, Mar 8, 2005

Filed:

Jan 31, 2003

Appl. No.:

10/357166

Inventors:

Kenneth G. Richardson - Erie CO, US

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H03F003/04

US Classification:

330288, 330296

Abstract:

An amplifier for a differential signal drain is able to amplify a signal over a frequency range and boost the signal within a specified frequency range. A resistor is placed between the drain and gate of the first transistor of a cascode amplifier and can be selected to provide additional signal boost at a specified input frequency. An additional input transistor may be added to provide a stepped amplification over the frequency range. The amplifier is further able to reject common mode signals by using regulating transistors.

US Patent:

6954107, Oct 11, 2005

Filed:

Dec 23, 2004

Appl. No.:

11/021579

Inventors:

Kenneth G. Richardson - Erie CO, US

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H03F003/04

US Classification:

330288, 330296

Abstract:

An amplifier for a differential signal drain is able to amplify a signal over a frequency range and boost the signal within a specified frequency range. A resistor is placed between the drain and gate of the first transistor of a cascode amplifier and can be selected to provide additional signal boost at a specified input frequency. An additional input transistor may be added to provide a stepped amplification over the frequency range. The amplifier is further able to reject common mode signals by using regulating transistors.

US Patent:

7170727, Jan 30, 2007

Filed:

Jan 31, 2003

Appl. No.:

10/357044

Inventors:

Kenneth Richardson - Erie CO, US

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H02H 3/22

US Classification:

361 56, 361111

Abstract:

An input pad for a differential current input to an integrated circuit contains a switchable and tunable input impedance. The input pad also contains ESD protection and common mode rejection while maintaining low capacitance. The common mode rejection comprises two resistors that combine to remove the common mode current from the two input lines, produce a reference current, and drive two output transistors that cancel the common mode current from the outputs.

US Patent:

8134188, Mar 13, 2012

Filed:

Aug 14, 2007

Appl. No.:

11/838546

Inventors:

Kenneth G. Richardson - Erie CO, US
Michael Straub - Longmont CO, US

Assignee:

AGERE Systems Inc. - Allentown PA

International Classification:

H01L 29/80

US Classification:

257256, 257202, 257272, 257E29024

Abstract:

Various embodiments of the present invention provide circuits and methods for improved FET matching. As one example, such methods may include providing two or more transistors. Each of the transistors includes a channel that varies in cross-sectional width from the source to the drain, and the transistors are matched one to another.

US Patent:

8440512, May 14, 2013

Filed:

Feb 8, 2012

Appl. No.:

13/368985

Inventors:

Kenneth G. Richardson - Erie CO, US
Michael Straub - Longmont CO, US

Assignee:

AGERE Systems Inc. - Allentown PA

International Classification:

H01L 21/00

US Classification:

438163, 257287

Abstract:

The present inventions are related to systems and methods for pre-equalizer noise suppression in a data processing system. As an example, a data processing system is discussed that includes: a sample averaging circuit, a selector circuit, an equalizer circuit, and a mark detector circuit. The sample averaging circuit is operable to average corresponding data samples from at least a first read of a codeword and a second read of the codeword to yield an averaged output based at least in part on a framing signal. The selector circuit is operable to select one of the averaged output and the first read of the codeword as a selected output. The equalizer circuit is operable to equalize the selected output to yield an equalized output, and the mark detector circuit is operable to identify a location mark in the equalized output to yield the framing signal.