Kenneth D Shepard

US Patent:

6453444, Sep 17, 2002

Filed:

Feb 2, 2000

Appl. No.:

09/496805

Inventors:

Kenneth L. Shepard - Ossining NY

Assignee:

The Trustees of Columbia University in the City of New York - New York NY

International Classification:

G06F 1750

US Classification:

716 2

Abstract:

Disclosed is an approximate inductance extraction method that can be practically applied to full-chip inductance extraction of complex integrated circuits. The method results in a positive semi-definite inductance matrix and achieves sparsity of the inductance matrix by breaking inductive couplings between power-ground lines and signal lines and by using a set of geometry based decomposition rules to eliminate insignificant coupling interactions between signal lines. By taking advantage of the ever-present availability of power-ground lines as high frequency current returns while preserving inductive coupling between signal lines, the disclosed method has demonstrated higher efficiency and accuracy than other inductance matrix sparsification techniques.

US Patent:

7015765, Mar 21, 2006

Filed:

Jul 26, 2004

Appl. No.:

10/898743

Inventors:

Kenneth Shepard - Ossining NY, US
Steven Chan - Yonkers NY, US

Assignee:

The Trustees of Columbia in the City of New York - New York NY

International Classification:

H03B 5/18
G06F 1/04

US Classification:

331117D, 331 2, 331 36 C, 331 56, 331 96, 331177 V, 713500

Abstract:

A circuit for distributing a clock signal in an integrated circuit includes a capacitive clock distribution circuit having at least conductor therein. At least one inductor is formed in a metal layer of the integrated circuit and is coupled to the clock distribution circuit. The inductor, generally in the form of a number of spiral inductors distributed throughout the integrated circuit, provides an inductance value selected to resonate with the capacitive clock distribution circuit. By operating the clock distribution circuit at resonance, power dissipation is reduced while skew and jitter performance can be improved.

US Patent:

7103522, Sep 5, 2006

Filed:

Jun 9, 2000

Appl. No.:

09/591270

Inventors:

Kenneth Shepard - Ossining NY, US

Assignee:

The Trustees of Columbia University in the City of New York - New York NY

International Classification:

G06F 17/50

US Classification:

703 14, 703 13, 716 4, 716 5

Abstract:

Techniques for estimating a body voltage of one or more transistors which form digital partially depleted silicon-on-insulator circuit, and for using estimated voltages to analyze electrical properties of the circuit, are disclosed. In one technique, device models are obtained and abstracted to generate simplified electrical descriptions of the transistors. The circuit topology is checked to generate sets of accessible states for the transistors that are indicative of whether a connection between a source or a drain of a transistor and either a power supply or ground exists. Next, sets of reference state body voltage minima and reference state body voltage maxima are determined for each of the transistors based on corresponding simplified electrical descriptions and corresponding sets of accessible states. Finally, a target state body voltage minima and a target state body voltage maxima are ascertained, one for each transistor, based on the determined sets of reference state body voltage minima and reference state body voltage maxima.

US Patent:

7145408, Dec 5, 2006

Filed:

Jan 13, 2003

Appl. No.:

10/501278

Inventors:

Kenneth Shepard - Ossining NY, US
Steven Chan - Yonkers NY, US

Assignee:

The Trustees of Columbia University in the City of New York - New York NY

International Classification:

H03B 5/12

US Classification:

331117D, 337117 R, 337117 FE, 337167, 337117 DP

Abstract:

A circuit for distributing a clock signal in an integrated circuit includes a capacitive clock distribution circuit. At least one additional inductor is formed in a metal layer of the integrated circuit and is coupled to the clock distribution circuit. The inductor, which may distributed throughout the integrated circuit, has an inductance value selected to resonate with impedance of the capacitive clock distribution circuit. By operating the clock distribution circuit at resonance, power dissipation is reduced while skew and jitter performance can be improved.

US Patent:

7329968, Feb 12, 2008

Filed:

May 10, 2004

Appl. No.:

10/842149

Inventors:

Kenneth Shepard - Ossining NY, US
Saravanan Rajapandian - New York NY, US

Assignee:

The Trustees of Columbia University in the City of New York - New York NY

International Classification:

H02J 1/10

US Classification:

307 18

Abstract:

An integrated circuit with multiple supply voltage domains includes a first domain and a second domain of electrical components. The first domain receives current from a first voltage rail and discharges electrical current to a second voltage rail. A second domain of electrical components receives current from the second voltage rail and discharges electrical current to a third voltage rail at a third voltage. An external voltage source provides a supply voltage across the first voltage rail and the third voltage rail. The integrated circuit further includes a regulator for regulating the second voltage rail. The circuit domains are divided into granules that can be multiplexed between domains when the supply voltage fluctuations are too large and too long for the regulator to handle. This concept may be extended to include additional domains of electrical components.

US Patent:

7548094, Jun 16, 2009

Filed:

Jan 17, 2007

Appl. No.:

11/654286

Inventors:

Kenneth L. Shepard - Ossining NY, US
Anup P. Jose - Acton MA, US

Assignee:

The Trustees of Columbia University in the City of New York - New York NY

International Classification:

H03K 19/0175
H03K 19/02

US Classification:

326 82, 326135

Abstract:

Systems and methods for on-chip signaling are disclosed. In some embodiments, an integrated circuit having on-chip signaling between a first component and a second component includes, a differential interconnect capable of coupling the first component to the second component, a driver capable of being coupled to the first component that sends data on the differential interconnect, a receiver capable of being coupled to the second component that receives the data, and a plurality of negative impedance converters capable of being coupled to the differential interconnect that provide loss compensation.

US Patent:

7738086, Jun 15, 2010

Filed:

May 4, 2007

Appl. No.:

11/800468

Inventors:

Kenneth L. Shepard - Ossining NY, US
Rastislav Levicky - Irvington NY, US
George Patounakis - North Brunswick NJ, US

Assignee:

The Trustees of Columbia University in the City of New York - New York NY

International Classification:

G01N 21/00

US Classification:

356 73, 356317, 356318, 436172, 435 4, 435 6

Abstract:

An active CMOS biosensor chip for fluorescent-based detection is provided that enables time-gated, time-resolved fluorescence spectroscopy. In one embodiment, analytes are loaded with fluorophores that are bound to probe molecules immobilized on the surface of the chip. Photodiodes and other circuitry in the chip are used to measure the fluorescent intensity of the fluorophore at different times. These measurements are then averaged to generate a representation of the transient fluorescent decay response unique to the fluorophores. In addition to its low-cost, compact form, the biosensor chip provides capabilities beyond those of macroscopic instrumentation by enabling time-gated operation for background rejection, easing requirements on optical filters, and by characterizing fluorescence lifetime, allowing for a more detailed characterization of fluorophore labels and their environment. The biosensor chip can be used for a variety of applications including biological, medical, in-the-field applications, and fluorescent lifetime imaging applications.

US Patent:

7880551, Feb 1, 2011

Filed:

Dec 29, 2006

Appl. No.:

12/159750

Inventors:

Steven Chan - Yonkers NY, US
Kenneth L. Shepard - Ossining NY, US
Zheng Xu - Staten Island NY, US

Assignee:

The Trustees of Columbia University in the City of New York - New York NY

International Classification:

G06F 1/00
H03B 5/00
H03B 5/18
H03L 5/00
H03L 7/00
H03L 7/099
H03L 7/24

US Classification:

331 55, 331 2, 331 96, 331117 D, 331179, 331183, 713500, 713503

Abstract:

Systems and methods for distributing a clock signal are disclosed. In some embodiments, systems for distributing a clock signal include a plurality of resonant oscillators, each comprising an inductor; and a differential clock grid that distributes the clock signal. The differential clock grid is coupled to the plurality of resonant oscillators and the clock signal, and the inductances of the inductors are configured such that a resonant frequency of the plurality of resonant oscillators is substantially equal to the frequency of the clock signal.