Kenneth J Wallace

US Patent:

60522984, Apr 18, 2000

Filed:

Mar 3, 1999

Appl. No.:

9/261783

Inventors:

Kenneth Andrew Wallace - Lewis Center OH
Gueorgui I. Mantov - Lexington OH

Assignee:

Peco II, Inc. - Galion OH

International Classification:

H02M 324

US Classification:

363 95

Abstract:

A noise suppression circuit for use with a DC/DC converter having an output and an input responsive at least in part to the output of the converter is provided. The noise suppression circuit includes multiple parallel feedback loops, wherein the first feedback sets the steady state nominal output voltage, the second feedback loop prevents the output voltage from exceeding a predefined high voltage level, and the third feedback loop prevents the output voltage from decreasing below a predefined low voltage level. In some embodiments, the first, second, and third feedback loops comprise a operational amplifier, a diode, and an internal feedback loop, wherein the internal feedback loops of each of these loops share a common node. The common node configuration provides the circuit with quick transitions between output voltage states and dynamic regulation of the DC/DC converter output voltage.

US Patent:

59630787, Oct 5, 1999

Filed:

Jan 26, 1998

Appl. No.:

9/013132

Inventors:

Kenneth Andrew Wallace - Lewis Center OH

Assignee:

Peco II, Inc. - Galion OH

International Classification:

H03K 1760

US Classification:

327432

Abstract:

A FET drive circuit is disclosed. The disclosed drive circuit develops a unipolar voltage from a bi-polar source voltage and facilitates fast turn-off of the driven FET. Preferably, the drive circuit includes a first diode having a first reverse recovery time, a transistor, and a second diode having a second reverse recovery time which is longer than the first reverse recovery time.

US Patent:

61186805, Sep 12, 2000

Filed:

May 28, 1999

Appl. No.:

9/322726

Inventors:

Kenneth Andrew Wallace - Lewis Center OH
Gueorgui I. Mantov - Lexington OH
Jon Drew Karnes - Galion OH
John Roller - Galion OH

Assignee:

PECO II - Galion OH

International Classification:

H02M 700

US Classification:

363 71

Abstract:

Methods and apparatus are disclosed for achieving load balance between parallel inverters in an AC power supply. Load balancing reduces undesirable cross conduction current between the parallel inverters. Load balancing and the resulting reduction in cross conduction current are achieved without the need for common control circuitry between the parallel inverters. Thus, the single-fault protection offered by redundant parallel inverters is not compromised by the disclosed load balancing techniques.

US Patent:

59333383, Aug 3, 1999

Filed:

Oct 14, 1997

Appl. No.:

8/949874

Inventors:

Kenneth Andrew Wallace - Lewis Center OH

Assignee:

Peco II, Inc. - Galion OH

International Classification:

H02M 318

US Classification:

363 61

Abstract:

A rectifying circuit comprising first and second current doublers is disclosed. In some embodiments, the first and second current doublers are connected in series. In other embodiments, the current doublers are connected in parallel. In phase pairs of inductors can share a common core to reduce parts and ensure voltage balance.