Kenneth Craig Ward

US Patent:

D467374, Dec 17, 2002

Filed:

May 8, 2002

Appl. No.:

29/160303

Inventors:

Gregory G. Kuelbs - Westlake TX
Kenneth M. Ward - Azle TX

Assignee:

World Factory, Inc. - Southlake TX

International Classification:

2602

US Classification:

D26 40

US Patent:

7083409, Aug 1, 2006

Filed:

Aug 1, 2002

Appl. No.:

10/211055

Inventors:

Gregory G. Kuelbs - Westlake TX, US
Kenneth M. Ward - Azle TX, US

Assignee:

World Factory, Inc. - Coppell TX

International Classification:

F23D 3/18

US Classification:

431321, 431323, 431310, 431304

Abstract:

An oil burning lamp has a fuel reservoir, a fuel expansion chamber releasably and sealingly coupled to the fuel reservoir, a burner assembly coupled to the fuel expansion chamber, and an adjustable wick. If the fuel in the fuel reservoir undergoes thermal expansion, it flows into the fuel expansion chamber, thereby preventing fuel leaks and spills. In the preferred embodiment, the burner assembly is permanently coupled to the fuel expansion chamber, thereby preventing users from refueling the lamp while the lamp is burning. The fuel expansion chamber also serves as an overflow fuel chamber, so that if the lamp is inadvertently knocked over, the fuel will flow into the fuel expansion chamber, not out of the lamp.

US Patent:

7409589, Aug 5, 2008

Filed:

May 27, 2005

Appl. No.:

11/140648

Inventors:

Michael James Mack - Round Rock TX, US
Kenneth Lundy Ward - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 11/00

US Classification:

714 15, 714 10, 712228

Abstract:

A method and apparatus are provided for reducing the number of cycles required to checkpoint instructions in a multi-threaded microprocessor that has dispatch group checkpointing. A determination is made in a first stage of a checkpoint pipeline whether checkpointing can occur for a group of instructions. The results of processing the group of instructions flow to a second stage of the checkpoint pipeline regardless of whether the group of instructions is ready to checkpoint. If the group of instructions is ready to checkpoint, the group of instructions is checkpointed in a third stage of the checkpoint pipeline.

US Patent:

7487377, Feb 3, 2009

Filed:

Feb 9, 2005

Appl. No.:

11/054294

Inventors:

Scott Barnett Swaney - Catskill NY, US
Kenneth Lundy Ward - Austin TX, US
Tobias Webel - Schwaebisch-Gmuend, DE
Ulrich Weiss - Holzgerlingen, DE
Matthias Woehrle - Boeblingen, DE

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 13/42

US Classification:

713401, 713375, 713400

Abstract:

Redundant time-of-day (TOD) oscillators are aligned, within a master oscillator path, to local logic oscillator and used to create independent step-sync signals. A step checker validates and provides selection signals to identify which of the TOD oscillators operates according to a criterion. Independent step-sync signals are transmitted to several sibling chips. Local step and sync signals are delayed to arrive at TOD register nearly synchronous with TOD registers in sibling chips. A slave oscillator path may be used to select time signals generated in a sibling chip, whereby the master oscillator path is deselected. A primary control register set may be used to configure which among several chips is a master chip using the master oscillator path. All remaining chips are slave chips. All segments of the topology are redundant.

US Patent:

7526583, Apr 28, 2009

Filed:

Jun 23, 2005

Appl. No.:

11/165484

Inventors:

Michael J. Mack - Round Rock TX, US
Kenneth L. Ward - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 3/00
G06F 5/00

US Classification:

710 54, 714724

Abstract:

A method of checkpointing a microprocessor by providing, in parallel, a current read value from a queue and a next read value from the queue, and then selectively passing one of the current read value and next read value to a capture latch based on an instruction completion signal. The capture latch can directly drive the checkpoint register circuitry in the recovery unit of the microprocessor. If the queue is empty, a pair of multiplexers connected to the input of the register queue array are used to pass the input data value. The instruction completion signal may indicate whether all instructions in an instruction group have successfully completed.

US Patent:

7603497, Oct 13, 2009

Filed:

Jan 27, 2009

Appl. No.:

12/360116

Inventors:

Michael J. Mack - Round Rock TX, US
Kenneth L. Ward - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 3/00
G06F 5/00

US Classification:

710 54, 714724

Abstract:

A method of checkpointing a microprocessor by providing, in parallel, a current read value from a queue and a next read value from the queue, and then selectively passing one of the current read value and next read value to a capture latch based on an instruction completion signal. The capture latch can directly drive the checkpoint register circuitry in the recovery unit of the microprocessor. If the queue is empty, a pair of multiplexers connected to the input of the register queue array are used to pass the input data value. The instruction completion signal may indicate whether all instructions in an instruction group have successfully completed.

US Patent:

7761726, Jul 20, 2010

Filed:

May 7, 2008

Appl. No.:

12/116652

Inventors:

Scott Barnett Swaney - Catskill NY, US
Kenneth Lundy Ward - Austin TX, US
Tobias Webel - Schwaebisch-Gmuend, DE
Ulrich Weiss - Holzgerlingen, DE
Matthias Woehrle - Boeblingen, GR

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1/12

US Classification:

713400, 713375, 713401

Abstract:

Redundant time-of-day (TOD) oscillators are aligned, within a master oscillator path, to local logic oscillator and used to create independent step-sync signals. A step checker validates and provides selection signals to identify which of the TOD oscillators operates according to a criterion. Independent step-sync signals are transmitted to several sibling chips. Local step and sync signals are delayed to arrive at TOD register nearly synchronous with TOD registers in sibling chips. A slave oscillator path may be used to select time signals generated in a sibling chip, whereby the master oscillator path is deselected. A primary control register set may be used to configure which among several chips is a master chip using the master oscillator path. All remaining chips are slave chips. All segments of the topology are redundant.

US Patent:

7865758, Jan 4, 2011

Filed:

Jun 16, 2008

Appl. No.:

12/140028

Inventors:

Scott Barnett Swaney - Catskill NY, US
Kenneth Lundy Ward - Austin TX, US
Tobias Webel - Schwaebisch-Gmuend, DE
Ulrich Weiss - Holzgerlingen, DE
Matthias Woehrle - Boeblingen, GR

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1/12

US Classification:

713500, 713400, 713401

Abstract:

Redundant time-of-day (TOD) oscillators are aligned, within a master oscillator path, to local logic oscillator and used to create independent step-sync signals. A step checker validates and provides selection signals to identify which of the TOD oscillators operates according to a criterion. Independent step-sync signals are transmitted to several sibling chips. Local step and sync signals are delayed to arrive at TOD register nearly synchronous with TOD registers in sibling chips. A slave oscillator path may be used to select time signals generated in a sibling chip, whereby the master oscillator path is deselected. A primary control register set may be used to configure which among several chips is a master chip using the master oscillator path. All remaining chips are slave chips. All segments of the topology are redundant.