Kenneth C Ward

Address:

1723 Brandenburg Dr, Hl Cntry Vlg, TX 78232

Phone:

(210)4942957

VIN:

4T1BE46K87U666662

Make:

TOYOTA

Model:

CAMRY

Year:

2007

US Patent:

7409589, Aug 5, 2008

Filed:

May 27, 2005

Appl. No.:

11/140648

Inventors:

Michael James Mack - Round Rock TX, US
Kenneth Lundy Ward - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 11/00

US Classification:

714 15, 714 10, 712228

Abstract:

A method and apparatus are provided for reducing the number of cycles required to checkpoint instructions in a multi-threaded microprocessor that has dispatch group checkpointing. A determination is made in a first stage of a checkpoint pipeline whether checkpointing can occur for a group of instructions. The results of processing the group of instructions flow to a second stage of the checkpoint pipeline regardless of whether the group of instructions is ready to checkpoint. If the group of instructions is ready to checkpoint, the group of instructions is checkpointed in a third stage of the checkpoint pipeline.

US Patent:

7487377, Feb 3, 2009

Filed:

Feb 9, 2005

Appl. No.:

11/054294

Inventors:

Scott Barnett Swaney - Catskill NY, US
Kenneth Lundy Ward - Austin TX, US
Tobias Webel - Schwaebisch-Gmuend, DE
Ulrich Weiss - Holzgerlingen, DE
Matthias Woehrle - Boeblingen, DE

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 13/42

US Classification:

713401, 713375, 713400

Abstract:

Redundant time-of-day (TOD) oscillators are aligned, within a master oscillator path, to local logic oscillator and used to create independent step-sync signals. A step checker validates and provides selection signals to identify which of the TOD oscillators operates according to a criterion. Independent step-sync signals are transmitted to several sibling chips. Local step and sync signals are delayed to arrive at TOD register nearly synchronous with TOD registers in sibling chips. A slave oscillator path may be used to select time signals generated in a sibling chip, whereby the master oscillator path is deselected. A primary control register set may be used to configure which among several chips is a master chip using the master oscillator path. All remaining chips are slave chips. All segments of the topology are redundant.

US Patent:

7526583, Apr 28, 2009

Filed:

Jun 23, 2005

Appl. No.:

11/165484

Inventors:

Michael J. Mack - Round Rock TX, US
Kenneth L. Ward - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 3/00
G06F 5/00

US Classification:

710 54, 714724

Abstract:

A method of checkpointing a microprocessor by providing, in parallel, a current read value from a queue and a next read value from the queue, and then selectively passing one of the current read value and next read value to a capture latch based on an instruction completion signal. The capture latch can directly drive the checkpoint register circuitry in the recovery unit of the microprocessor. If the queue is empty, a pair of multiplexers connected to the input of the register queue array are used to pass the input data value. The instruction completion signal may indicate whether all instructions in an instruction group have successfully completed.

US Patent:

7603497, Oct 13, 2009

Filed:

Jan 27, 2009

Appl. No.:

12/360116

Inventors:

Michael J. Mack - Round Rock TX, US
Kenneth L. Ward - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 3/00
G06F 5/00

US Classification:

710 54, 714724

Abstract:

A method of checkpointing a microprocessor by providing, in parallel, a current read value from a queue and a next read value from the queue, and then selectively passing one of the current read value and next read value to a capture latch based on an instruction completion signal. The capture latch can directly drive the checkpoint register circuitry in the recovery unit of the microprocessor. If the queue is empty, a pair of multiplexers connected to the input of the register queue array are used to pass the input data value. The instruction completion signal may indicate whether all instructions in an instruction group have successfully completed.

US Patent:

7761726, Jul 20, 2010

Filed:

May 7, 2008

Appl. No.:

12/116652

Inventors:

Scott Barnett Swaney - Catskill NY, US
Kenneth Lundy Ward - Austin TX, US
Tobias Webel - Schwaebisch-Gmuend, DE
Ulrich Weiss - Holzgerlingen, DE
Matthias Woehrle - Boeblingen, GR

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1/12

US Classification:

713400, 713375, 713401

Abstract:

Redundant time-of-day (TOD) oscillators are aligned, within a master oscillator path, to local logic oscillator and used to create independent step-sync signals. A step checker validates and provides selection signals to identify which of the TOD oscillators operates according to a criterion. Independent step-sync signals are transmitted to several sibling chips. Local step and sync signals are delayed to arrive at TOD register nearly synchronous with TOD registers in sibling chips. A slave oscillator path may be used to select time signals generated in a sibling chip, whereby the master oscillator path is deselected. A primary control register set may be used to configure which among several chips is a master chip using the master oscillator path. All remaining chips are slave chips. All segments of the topology are redundant.

US Patent:

7865758, Jan 4, 2011

Filed:

Jun 16, 2008

Appl. No.:

12/140028

Inventors:

Scott Barnett Swaney - Catskill NY, US
Kenneth Lundy Ward - Austin TX, US
Tobias Webel - Schwaebisch-Gmuend, DE
Ulrich Weiss - Holzgerlingen, DE
Matthias Woehrle - Boeblingen, GR

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1/12

US Classification:

713500, 713400, 713401

Abstract:

Redundant time-of-day (TOD) oscillators are aligned, within a master oscillator path, to local logic oscillator and used to create independent step-sync signals. A step checker validates and provides selection signals to identify which of the TOD oscillators operates according to a criterion. Independent step-sync signals are transmitted to several sibling chips. Local step and sync signals are delayed to arrive at TOD register nearly synchronous with TOD registers in sibling chips. A slave oscillator path may be used to select time signals generated in a sibling chip, whereby the master oscillator path is deselected. A primary control register set may be used to configure which among several chips is a master chip using the master oscillator path. All remaining chips are slave chips. All segments of the topology are redundant.

US Patent:

7870406, Jan 11, 2011

Filed:

Feb 3, 2005

Appl. No.:

11/050325

Inventors:

Richard Louis Arndt - Austin TX, US
Balaram Sinharoy - Poughkeepsie NY, US
Scott Barnett Swaney - Catskill NY, US
Kenneth Lundy Ward - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1/00

US Classification:

713322

Abstract:

Mechanism for accurately measuring useful capacity of a processor allocated to each thread in a simultaneously multi-threading data processing system. Instructions dispatched from multiple threads are executed by the processor on a same clock cycle. A determination is made whether Time Base (TB) register bit () is changing. A dispatch charge value is determined for each thread, and added to the Processor Utilization Resource Register for each thread when TB bit () changes.

US Patent:

58058362, Sep 8, 1998

Filed:

Dec 10, 1996

Appl. No.:

8/762901

Inventors:

Steven Russell Barnhart - Austin TX
Amit Sumanlal Shah - Round Rock TX
Kenneth Lundy Ward - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1336

US Classification:

395287

Abstract:

An apparatus for equalizing grants of a primary bus to a plurality of primary devices and secondary devices is provided. The apparatus comprises a primary bus bridge to arbitrate grants of the primary bus among a plurality of primary devices attached to the primary bus and a secondary bus bridge to arbitrate grants of the primary bus among a plurality of secondary devices attached to a secondary bus. A logic device is also provided to equalize grants of the primary bus to the primary and the secondary devices.