Kent Marion Jaeger

US Patent:

20090289716, Nov 26, 2009

Filed:

May 23, 2008

Appl. No.:

12/154648

Inventors:

Kent Jaeger - Cary IL, US
Lawrence E. Connell - Naperville IL, US

International Classification:

H03F 3/45

US Classification:

330261

Abstract:

Methods and corresponding systems for amplifying an input signal include inputting first and second differential input signals into first and second circuit legs, respectively, wherein the first circuit leg includes a first transistor coupled in series with a first variable current source, and wherein the second circuit leg includes a second transistor coupled in series with a second variable current source. The first and second variable current sources are dynamically set to provide first and second bias currents in response to the first and second differential input signals, wherein the first bias current is set inversely proportional to the second bias current. The first and second bias currents are sunk in the first and second circuit legs, respectively. First and second differential output signals are output from the first and second circuit legs, respectively.

US Patent:

20210099131, Apr 1, 2021

Filed:

Nov 5, 2020

Appl. No.:

17/090254

Inventors:

- Shenzhen, CN
Kent Jaeger - Cary IL, US

Assignee:

Huawei Technologies Co., Ltd. - Shenzhen

International Classification:

H03D 7/14
H03D 7/16
H04B 1/30
H03F 1/32
H03F 1/30

Abstract:

The disclosure relates to technology for shifting a frequency range of a signal. In one aspect, a circuit comprises a frequency mixer, a frequency synthesizer configured to generate an oscillator signal, a programmable driver, and a controller. The programmable driver is configured to receive the oscillator signal from the frequency synthesizer and to provide the oscillator signal to the oscillator input of the frequency mixer. The programmable driver is configured to have a variable drive strength. The controller is configured to control the drive strength of the programmable driver based on a frequency of the oscillator signal to adjust a rise time and a fall time of the oscillator signal at the oscillator input of the frequency mixer.

US Patent:

20200321479, Oct 8, 2020

Filed:

Mar 9, 2020

Appl. No.:

16/813702

Inventors:

- Plano TX, US
Lawrence E. Connell - Naperville IL, US
Kent Jaeger - Cary IL, US
Matthew Richard Miller - Arlington Heights IL, US

Assignee:

Futurewei Technologies, Inc. - Plano TX

International Classification:

H01L 29/93
H01L 29/66
H01L 29/94
H01L 27/08
H01L 29/10

Abstract:

Embodiments are provided herein for low loss coupling capacitor structures. The embodiments include a n-type varactor (NVAR) configuration and p-type varactor (PVAR) configuration. The structure in the NVAR configuration comprises a p-doped semiconductor substrate (Psub), a deep n-doped semiconductor well (DNW) in the Psub, and a p-doped semiconductor well (P well) in the DNW. The circuit structure further comprises a source terminal of a p-doped semiconductor material within P well, and a drain terminal of the p-doped semiconductor material within the P well. Additionally, the circuit structure comprises an insulated gate on the surface of the P well, a metal pattern comprising a plurality of layers of metal lines, and a plurality of vias through the metal lines. The vias are contacts connecting the metal lines to the gate, the source terminal, and the drain terminal.

US Patent:

20180090627, Mar 29, 2018

Filed:

Dec 4, 2017

Appl. No.:

15/830927

Inventors:

- Plano TX, US
Lawrence Connell - Naperville IL, US
Kent Jaeger - Cary IL, US
Matthew Richard Miller - Arlington Heights IL, US

International Classification:

H01L 29/93
H01L 29/94
H01L 29/66
H01L 29/10

Abstract:

Embodiments are provided herein for low loss coupling capacitor structures. The embodiments include a n-type varactor (NVAR) configuration and p-type varactor (PVAR) configuration. The structure in the NVAR configuration comprises a p-doped semiconductor substrate (Psub), a deep n-doped semiconductor well (DNW) in the Psub, and a p-doped semiconductor well (P well) in the DNW. The circuit structure further comprises a source terminal of a p-doped semiconductor material within P well, and a drain terminal of the p-doped semiconductor material within the P well. Additionally, the circuit structure comprises an insulated gate on the surface of the P well, a metal pattern comprising a plurality of layers of metal lines, and a plurality of vias through the metal lines. The vias are contacts connecting the metal lines to the gate, the source terminal, and the drain terminal.

US Patent:

20160308073, Oct 20, 2016

Filed:

Apr 15, 2015

Appl. No.:

14/687549

Inventors:

- Plano TX, US
Lawrence Connell - Naperville IL, US
Kent Jaeger - Cary IL, US
Matthew Richard Miller - Arlington Heights IL, US

International Classification:

H01L 29/93
H01L 29/10

Abstract:

Embodiments are provided herein for low loss coupling capacitor structures. The embodiments include a n-type varactor (NVAR) configuration and p-type varactor (PVAR) configuration. The structure in the NVAR configuration comprises a p-doped semiconductor substrate (Psub), a deep n-doped semiconductor well (DNW) in the Psub, and a p-doped semiconductor well (P well) in the DNW. The circuit structure further comprises a source terminal of a p-doped semiconductor material within P well, and a drain terminal of the p-doped semiconductor material within the P well. Additionally, the circuit structure comprises an insulated gate on the surface of the P well, a metal pattern comprising a plurality of layers of metal lines, and a plurality of vias through the metal lines. The vias are contacts connecting the metal lines to the gate, the source terminal, and the drain terminal.

US Patent:

20140361814, Dec 11, 2014

Filed:

Jun 11, 2013

Appl. No.:

13/914809

Inventors:

- Plano TX, US
Brian T. Creed - Batavia IL, US
Daniel P. McCarthy - Elk Grove Village IL, US
Kent Jaeger - Cary IL, US

International Classification:

H03K 3/012
H03K 21/00

US Classification:

327115, 327215, 327214

Abstract:

An apparatus comprising a latch comprising a differential inverter configured to receive a differential input signal and generate a differential output signal, a pair of cross-coupled inverters coupled to the differential inverter, and a first clock switch configured to couple the differential inverter to a voltage source, a second clock switch configured to couple the differential inverter to a ground, wherein the first clock switch and the second clock switch are configured to receive a differential clock signal, and wherein the first clock switch and the second clock switch are both open or both closed depending on the differential clock signal.

US Patent:

20140361821, Dec 11, 2014

Filed:

Jul 3, 2013

Appl. No.:

13/934306

Inventors:

- Plano TX, US
Daniel P. McCarthy - Elk Grove Village IL, US
Brian T. Creed - Batavia IL, US
Kent Jaeger - Cary IL, US

International Classification:

H03K 3/012

US Classification:

327218

Abstract:

An apparatus comprising a latch comprising a differential inverter configured to receive a differential input signal and generate a differential output signal, a pair of cross-coupled inverters coupled to the differential inverter, and a first clock switch configured to couple the differential inverter to a voltage source, a second clock switch configured to couple the differential inverter to a ground, wherein the first clock switch and the second clock switch are configured to receive a differential clock signal, and wherein the first clock switch and the second clock switch are both open or both closed depending on the differential clock signal, a second latch, wherein the first latch and the second latch are configured as a frequency divider, and a logic circuit coupled to each latch, wherein the logic circuits are configured to generate both an in-phase reference output signal and a quadrature output signal.