Kent A Stange

US Patent:

7725215, May 25, 2010

Filed:

May 4, 2006

Appl. No.:

11/381608

Inventors:

Kent Stange - Phoenix AZ, US
Richard Hess - Glendale AZ, US
Gerald B Kelley - Glendale AZ, US
Randy Rogers - Phoenix AZ, US

Assignee:

Honeywell International Inc. - Morristown NJ

International Classification:

G06F 11/00
G06F 7/00
B64C 19/00

US Classification:

701 1, 701 3, 701 29, 701 31, 701 36, 244 751, 244194, 714 2, 714 11

Abstract:

A real-time multi-tasking digital control system with rapid recovery capability is disclosed. The control system includes a plurality of computing units comprising a plurality of redundant processing units, with each of the processing units configured to generate one or more redundant control commands. One or more internal monitors are employed for detecting data errors in the control commands. One or more recovery triggers are provided for initiating rapid recovery of a processing unit if data errors are detected. The control system also includes a plurality of actuator control units each in operative communication with the computing units. The actuator control units are configured to initiate a rapid recovery if data errors are detected in one or more of the processing units. A plurality of smart actuators communicates with the actuator control units, and a plurality of redundant sensors communicates with the computing units.

US Patent:

7765427, Jul 27, 2010

Filed:

May 4, 2006

Appl. No.:

11/381637

Inventors:

Kent Stange - Phoenix AZ, US
Richard Hess - Glendale AZ, US
Gerald B Kelley - Glendale AZ, US
Randy Rogers - Phoenix AZ, US

Assignee:

Honeywell International Inc. - Morristown NJ

International Classification:

G06F 11/00

US Classification:

714 10

Abstract:

A monitoring system and methods are provided for a distributed and recoverable digital control system. The monitoring system generally comprises two independent monitoring planes within the control system. The first monitoring plane is internal to the computing units in the control system, and the second monitoring plane is external to the computing units. The internal first monitoring plane includes two in-line monitors. The first internal monitor is a self-checking, lock-step-processing monitor with integrated rapid recovery capability. The second internal monitor includes one or more reasonableness monitors, which compare actual effector position with commanded effector position. The external second monitor plane includes two monitors. The first external monitor includes a pre-recovery computing monitor, and the second external monitor includes a post recovery computing monitor. Various methods for implementing the monitoring functions are also disclosed.

US Patent:

7793147, Sep 7, 2010

Filed:

Jul 18, 2006

Appl. No.:

11/458301

Inventors:

Kent Stange - Phoenix AZ, US
Richard Hess - Glendale AZ, US
Gerald B Kelley - Glendale AZ, US
Randy Rogers - Phoenix AZ, US

Assignee:

Honeywell International Inc. - Morristown NJ

International Classification:

G06F 11/00

US Classification:

714 13, 714 12, 714 16

Abstract:

A method for optimizing the use of digital computing resources to achieve reliability and availability of the computing resources is disclosed. The method comprises providing one or more processors with a recovery mechanism, the one or more processors executing one or more applications. A determination is made whether the one or more processors needs to be reconfigured. A rapid recovery is employed to reconfigure the one or more processors when needed. A computing system that provides reconfigurable and recoverable computing resources is also disclosed. The system comprises one or more processors with a recovery mechanism, with the one or more processors configured to execute a first application, and an additional processor configured to execute a second application different than the first application. The additional processor is reconfigurable with rapid recovery such that the additional processor can execute the first application when one of the one more processors fails.

US Patent:

7840316, Nov 23, 2010

Filed:

Dec 17, 2007

Appl. No.:

11/957665

Inventors:

Larry J. Yount - Scottsdale AZ, US
Gerald B. Kelley - Glendale AZ, US
Kent A. Stange - Phoenix AZ, US
Welsh C. Pond - Glendale AZ, US

Assignee:

Honeywell International Inc. - Morristown NJ

International Classification:

G01C 23/00

US Classification:

701 3, 701 4, 244194, 318564

Abstract:

An aircraft flight control surface actuation control system includes an actuator control unit and a flight control module. The actuator control unit includes at least two independent actuator control channels to generate limited authority flight control surface actuator commands based on pilot inceptor position signals and flight control augmentation data. The flight control module supplies the flight control augmentation data to each of the independent actuator control channels, determines operability of each of the actuator control channels and, based on the determined operability of each independent actuator control channel, selectively prevents one of the independent actuator control channels from supplying the limited authority flight control surface actuator commands. The flight control module may also generate full authority flight control surface actuator commands for supply to flight control surface actuators.

US Patent:

7971095, Jun 28, 2011

Filed:

Feb 16, 2005

Appl. No.:

11/058764

Inventors:

Richard Hess - Glendale AZ, US
Gerald B. Kelly - Glendale AZ, US
Randy Rogers - Phoenix AZ, US
Kent A. Stange - Phoenix AZ, US

Assignee:

Honeywell International Inc. - Morristown NJ

International Classification:

G06F 11/00

US Classification:

714 15

Abstract:

System and methods for providing a recoverable real time multi-tasking computer system are disclosed. In one embodiment, a system comprises a real time computing environment, wherein the real time computing environment is adapted to execute one or more applications and wherein each application is time and space partitioned. The system further comprises a fault detection system adapted to detect one or more faults affecting the real time computing environment and a fault recovery system, wherein upon the detection of a fault the fault recovery system is adapted to restore a backup set of state variables.

US Patent:

8260492, Sep 4, 2012

Filed:

May 4, 2006

Appl. No.:

11/381652

Inventors:

Kent Stange - Phoenix AZ, US
Richard Hess - Glendale AZ, US
Gerald B Kelley - Glendale AZ, US
Randy Rogers - Phoenix AZ, US

Assignee:

Honeywell International Inc. - Morristown NJ

International Classification:

G06F 11/08
G06F 11/20

US Classification:

701 343, 701 337, 714 15, 714 20, 714E11007, 714E1103, 714E11055

Abstract:

A method and system for redundancy management is provided for a distributed and recoverable digital control system. The method uses unique redundancy management techniques to achieve recovery and restoration of redundant elements to full operation in an asynchronous environment. The system includes a first computing unit comprising a pair of redundant computational lanes for generating redundant control commands. One or more internal monitors detect data errors in the control commands, and provide a recovery trigger to the first computing unit. A second redundant computing unit provides the same features as the first computing unit. A first actuator control unit is configured to provide blending and monitoring of the control commands from the first and second computing units, and to provide a recovery trigger to each of the first and second computing units. A second actuator control unit provides the same features as the first actuator control unit.

US Patent:

8560149, Oct 15, 2013

Filed:

Sep 20, 2012

Appl. No.:

13/623850

Inventors:

Kevin D. Vanderwerf - Oro Valley AZ, US
Kent Stange - Phoenix AZ, US
Scot Griffith - Glendale AZ, US

Assignee:

Honeywell International Inc. - Morristown NJ

International Classification:

G06F 19/00

US Classification:

701 15

Abstract:

Systems and methods for takeoff assistance and analysis are provided. In one embodiment, a takeoff ground roll assist system for an aircraft comprises: a runway centerline estimator, wherein the runway centerline estimator generates a virtual runway centerline estimate for a runway based on coordinates for the runway from a runway database; an (Inertial Navigation System) INS Output Filter and Fault Detector wherein the filtering of navigation measurements from an on-board inertial navigation system, using a runway centerline start point as established by activation of a pilot operated start point sensor occurs, a centerline tracking estimator coupled to receive a filtered output of the on-board inertial navigation system from the INS output filter and fault detector and to receive the virtual centerline estimate from the runway centerline estimator, wherein the centerline tracking estimator generates a centerline tracking feedback signal that varies as a function of a difference between an aircraft look-ahead point and the virtual runway centerline; and a takeoff criteria evaluator coupled to the runway centerline estimator and the centerline tracking estimator, wherein the takeoff criteria evaluator estimates a lateral deviation between the aircraft and an actual runway centerline for the runway based on an estimated navigation error component, the runway database error component, and a centerline tracking error component.

US Patent:

20100064092, Mar 11, 2010

Filed:

May 19, 2005

Appl. No.:

11/132860

Inventors:

Richard F. Hess - Glendale AZ, US
Kent A. Stange - Phoenix AZ, US

Assignee:

Honeywell International Inc. - Morristown NJ

International Classification:

G06F 12/00
G06F 12/02

US Classification:

711103, 711167, 711E12001, 711E12008

Abstract:

An interface between memories having different write times is described. The interface includes a latch for capturing address and data information during a memory access by a processor of a first memory device. The interface also includes an index counter for providing frame management. The interface also includes a variable identity array logic for determining what data is to be written into a second memory device and address generation logic to determine where the data is to be stored in the second memory device. Additionally, the interface includes data validity logic to ensure that the data being written into the second memory device is valid. As a result, the processor can operate in substantially real time and can restore itself after detecting an event upset using the data stored in the second memory device.