Kevin Kin Chan

US Patent:

6339002, Jan 15, 2002

Filed:

Feb 10, 2000

Appl. No.:

09/501226

Inventors:

Kevin K. Chan - Staten Island NY
Erin C. Jones - Tuckahoe NY
Paul M. Solomon - Yorktown Heights NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21336

US Classification:

438283, 438299

Abstract:

A method of forming a double gate metal-oxide-semiconductor field effect transistor (MOSFET). The method includes planarizing a backgate mesa stack of a backgate using chemical mechanical polishing (CMP) to isolate the backgate mesa. A topgate mesa stack is formed and patterned. The backgate is trimmed using the topgate as a mask to transfer a topgate pattern to the backgate. Then, the trimmed backgate is isolated. In one particular embodiment, CMP is used to isolate and planarize the trimmed backgate.

US Patent:

6350321, Feb 26, 2002

Filed:

Dec 8, 1998

Appl. No.:

09/207353

Inventors:

Kevin K. Chan - Staten Island NY
Christopher P. DEmic - Ossining NY
Raymond M. Sicina - Florida NY
Paul M. Kozlowski - Hopewell Junction NY
Margaret Manny - Mahopac NY
Sandip Tiwari - Ossining NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

C23C 1600

US Classification:

118719, 156345

Abstract:

A cluster system controls the interface properties of the films that deposit or grow on a silicon substrate. The system comprises a plurality of horizontal quartz chamber or tubes each of which can hold a large quantity of wafers, a transfer chamber and a load/unload chamber. Several process steps can be executed sequentially in different tubes without intermediate exposure to ambient air. A transfer chamber connects them and allows wafer transportation from one tube to another in an absolute controlled UHV environment which limits any contamination such as H O, to less than a monolayer level. In addition, each tube can be pumped down to UHV pressure regime to avoid further cross contamination between tubes or particle generation. Since some of the process requires elevated temperature, all wafers are placed vertically on the quartz boat to prevent any wafer sagging as in a vertical furnace. Furthermore, before any wafers are placed into the transfer chamber, they are loaded into a load/unload chamber, which is the sole connection to the ambient air, to be purged and pumped so as to minimize particles and contamination.

US Patent:

6365465, Apr 2, 2002

Filed:

Mar 19, 1999

Appl. No.:

09/272297

Inventors:

Kevin K. Chan - Staten Island NY
Guy M. Cohen - Mohegan Lake NY
Yuan Taur - Bedford NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21336

US Classification:

438283, 438157, 438300, 438269

Abstract:

A structure and a method of manufacturing a double-gate metal oxide semiconductor transistor includes forming a laminated structure having a single crystal silicon channel layer and insulating oxide and nitride layers on each side of the single crystal silicon channel, forming openings in the laminated structure, forming drain and source regions in the openings, doping the drain and source regions, forming a mask over the laminated structure, removing portions of the laminated structure not protected by the mask, removing the mask and the insulating oxide and nitride layers to leave the single crystal silicon channel layer suspended from the drain and source regions, forming an oxide layer to cover the drain and source regions and the channel layer, and forming a double-gate conductor over the oxide layer such that the double-gate conductor includes a first conductor on a first side of the single crystal silicon channel layer and a second conductor on a second side of the single crystal silicon channel layer.

US Patent:

6399406, Jun 4, 2002

Filed:

Apr 23, 2001

Appl. No.:

09/840264

Inventors:

Kevin K. Chan - Staten Island NY
Leathen Shi - Yorktown Heights NY
James L. Speidell - Pogughguag NY
James F. Ziegler - Yorktown Heights NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2100

US Classification:

438 28, 438 52, 438 95, 257415, 216 2

Abstract:

Communication signal mixing and filtering systems and methods utilizing an encapsulated micro electro-mechanical system (MEMS) device. Furthermore, disclosed is a method of fabricating a simple, unitarily constructed micro electromechanical system (MEMS) device which combines the steps of signal mixing and filtering, and which is smaller, less expensive and more reliable in construction and operation than existing devices currently employed in the technology.

US Patent:

6444578, Sep 3, 2002

Filed:

Feb 21, 2001

Appl. No.:

09/791024

Inventors:

Cyril Cabral, Jr. - Ossining NY
Roy Arthur Carruthers - Stormville NY
Kevin K. Chan - Staten Island NY
Guy M. Cohen - Mohegan Lake NY
Kathryn Wilder Guarini - Yorktown Heights NY
James M. Harper - Yorktown Heights NY
Christian Lavoie - Ossining NY
Paul M. Solomon - Yorktown Heights NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2144

US Classification:

438682, 438655, 438597, 438630

Abstract:

The present invention relates to a method of reducing Si consumption during a self-aligned silicide process which employs a MâSi or MâSiâGe alloy, where M is Co, Ni or CoNi and a blanket layer of Si. The present invention is particularly useful in minimizing Si consumption in shallow junction and thin silicon-on-insulator (SOI) electronic devices.

US Patent:

6448131, Sep 10, 2002

Filed:

Aug 14, 2001

Appl. No.:

09/929182

Inventors:

Cyril Cabral, Jr. - Ossining NY
Kevin K. Chan - Staten Island NY
Guy M. Cohen - Mohegan Lake NY
Ramachandra Divakaruni - Somers NY
Christian Lavoie - Ossining NY
Fenton R. McFeely - Ossining NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 218242

US Classification:

438243, 438386, 438964

Abstract:

A method for increasing the trench capacitor surface area is provided. The method, which utilizes a metal silicide to roughen the trench walls, increases capacitance due to the increase in the trench surface area after the silicide has been removed. The roughening of the trench walls can be controlled by varying one or more of the following parameters: the density of the metal, the metal film thickness, the silicide phase, and the choice of the metal. Once the metal is deposited in the trench, the method is self-limited. Shrinking the trench to its original width can be obtained by subsequent silicon deposition or by diffusion of silicon from a cap layer through the silicide.

US Patent:

6555880, Apr 29, 2003

Filed:

Jun 7, 2001

Appl. No.:

09/875187

Inventors:

Cyril Cabral, Jr. - Ossining NY
Kevin Kok Chan - Staten Island NY
Guy Moshe Cohen - Mohegan Lake NY
Kathryn Wilder Guarini - Yorktown Heights NY
Christian Lavoie - Ossining NY
Ronnen Andrew Roy - Ossining NY
Paul Michael Solomon - Yorktown Heights NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 31119

US Classification:

257384, 257382, 257754

Abstract:

A semiconductor structure includes raised source and drain regions, where the raised source and drain regions are facet free and unconstrained to have a shape conforming to a same crystallographic axes with respect to each other.

US Patent:

6579614, Jun 17, 2003

Filed:

Mar 23, 2001

Appl. No.:

09/814766

Inventors:

Kevin K. Chan - Staten Island NY
Erin C. Jones - Tuckahoe NY
Fenton R. McFeely - Ossining NY
Paul M. Solomon - Yorktown Heights NY
John J. Yurkas - Stamford CT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

B32B 900

US Classification:

428336, 428446, 428472, 428698, 428701

Abstract:

A method of treating structures (and the structure formed thereby), so as to prevent or retard the oxidation of a metal film, and/or prevent its delamination a substrate, includes providing a structure including a refractory metal film formed on a substrate, placing the structure into a vessel having a base pressure below approximately 10 torr, exposing the structure to a silane gas at a sufficiently high predetermined temperature and predetermined pressure to cause formation of a metal silicide layer on the refractory metal film, and exposing the structure to a second gas at a sufficiently high temperature and pressure to nitride the metal silicide layer into a nitrided layer.