Kevin Wayne Cook

US Patent:

20220416043, Dec 29, 2022

Filed:

Jun 25, 2021

Appl. No.:

17/359422

Inventors:

- Santa Clara CA, US
Anand S. MURTHY - Portland OR, US
Rushabh SHAH - Hillsboro OR, US
Kevin COOK - Portland OR, US
Anupama BOWONDER - Portland OR, US

International Classification:

H01L 29/423
H01L 29/06
H01L 29/786
H01L 29/08
H01L 29/417

Abstract:

Gate-all-around integrated circuit structures having confined epitaxial source or drain structures, are described. For example, an integrated circuit structure includes a plurality of nanowires above a sub-fin. A gate stack is over the plurality of nanowires and the sub-fin. Epitaxial source or drain structures are on opposite ends of the plurality of nanowires. The epitaxial source or drain structures comprise germanium and boron, and a protective layer comprising germanium, silicon and boron that at least partially covers the epitaxial source or drain structures to provide low contact resistivity.