Kevin B Glass

US Patent:

51990024, Mar 30, 1993

Filed:

Oct 1, 1990

Appl. No.:

7/591439

Inventors:

Michael A. G. Ang - Santa Clara CA
Kevin W. Glass - Sunnyvale CA
David J. Pilling - Los Altos Hills CA

Assignee:

Integrated Device Technology, Inc. - Santa Clara CA

International Classification:

G11C 700

US Classification:

3652335

Abstract:

For enabling a static, random-access-memory (500) bit lines (556 and 558) pre-charging circuit (518), employed is an address-change-detection circuit (510) having a plurality of address-change-detectors (570 and 572) each for detecting a change in an associated SRAM addressing signal and, driven by the address-change detectors (570 and 572), a pulse generator (700) driving the pre-charging circuit (518).

US Patent:

51480565, Sep 15, 1992

Filed:

Mar 27, 1991

Appl. No.:

7/676780

Inventors:

Kevin W. Glass - San Jose CA
Ashok Nagarajan - Fremont CA

Assignee:

MOS Electronics Corp. - Sunnyvale CA

International Classification:

H03K 1716
H03K 17687

US Classification:

307443

Abstract:

An output buffer circuit is disclosed that has optimized ground bounce characteristics while maintaining low propagation delay. The output buffer may be incorporated within an integrated circuit and may be embodied in either inverting or non-inverting and in either enabling and non-enabling configurations. The output buffer circuit includes a feedback means coupled to the output terminal of the output buffer and to a pull-down transistor. The feedback means provides a feedback voltage to the gate of the pull-down transistor to regulate the derivative of source current with respect to time. The feedback means includes a pair of field effect transistors and either an inverter gate or a NOR gate coupled across one of the feedback field effect transistors.

US Patent:

52606805, Nov 9, 1993

Filed:

Feb 13, 1992

Appl. No.:

7/835167

Inventors:

Kevin W. Glass - San Jose CA

Assignee:

MOS Electronics Corp. - Sunnyvale CA

International Classification:

G05B 103
G06F 702

US Classification:

3401462

Abstract:

A comparator circuit is provided that determines whether a given value is within a selected compare range. The comparator circuit electronically implements a Ling Adder algorithm to perform comparisons. The circuit operates at a high speed and requires fewer components compared to circuitry implementing a conventional carry look ahead algorithm. The circuit may be implemented in CMOS technology.

US Patent:

51929163, Mar 9, 1993

Filed:

Sep 20, 1991

Appl. No.:

7/763087

Inventors:

Kevin W. Glass - San Jose CA

Assignee:

MOS Electronics Corporation - Sunnyvale CA

International Classification:

H04K 513
G05F 500

US Classification:

328155

Abstract:

A charge-pump phase locked loop circuit is disclosed that is capable of operating with a high bandwidth while having a low associated noise jitter characteristic. In addition, the phase locked loop circuit has a high dynamic range and prevents against false locking to sub-harmonic frequencies. Furthermore, common mode noise rejection and other internal noise rejection characteristics are optimized.