Kevin A Hurd

US Patent:

20220365753, Nov 17, 2022

Filed:

Jul 29, 2022

Appl. No.:

17/816234

Inventors:

- Austin TX, US
Kevin Altair Hurd - Redwood City CA, US
Emil Talpes - San Mateo CA, US

International Classification:

G06F 7/575
G06T 1/20
G06F 15/80
G06F 7/52
G06F 7/50
G06N 3/063
G06N 3/04
G06F 7/544
G06F 17/16

Abstract:

Various embodiments of the disclosure relate to an accelerated mathematical engine. In certain embodiments, the accelerated mathematical engine is applied to image processing such that convolution of an image is accelerated by using a two-dimensional matrix processor comprising sub-circuits that include an ALU, output register and shadow register. This architecture supports a clocked, two-dimensional architecture in which image data and weights are multiplied in a synchronized manner to allow a large number of mathematical operations to be performed in parallel.

US Patent:

20220188123, Jun 16, 2022

Filed:

Oct 22, 2021

Appl. No.:

17/451989

Inventors:

- Palo Alto CA, US
Peter Joseph Bannon - Woodside CA, US
Kevin Altair Hurd - Redwood City CA, US

International Classification:

G06F 9/38
G06F 13/16
G06F 17/16
G06F 3/06
G06F 15/80

Abstract:

A microprocessor system comprises a computational array and a hardware arbiter. The computational array includes a plurality of computation units. Each of the plurality of computation units operates on a corresponding value addressed from memory. The hardware arbiter is configured to control issuing of at least one memory request for one or more of the corresponding values addressed from the memory for the computation units. The hardware arbiter is also configured to schedule a control signal to be issued based on the issuing of the memory requests.

US Patent:

20210240440, Aug 5, 2021

Filed:

Mar 26, 2021

Appl. No.:

17/214526

Inventors:

- Santa Clara CA, US
Dongdong Chen - Union City CA, US
Kevin Hurd - Santa Clara CA, US

International Classification:

G06F 7/487
G06F 9/30
G06F 7/544

Abstract:

An integrated circuit with specialized processing blocks is provided. A specialized processing block may be optimized for machine learning algorithms and may include a multiplier data path that feeds an adder data path. The multiplier data path may be decomposed into multiple partial product generators, multiple compressors, and multiple carry-propagate adders of a first precision. Results from the carry-propagate adders may be added using a floating-point adder of the first precision. Results from the floating-point adder may be optionally cast to a second precision that is higher or more accurate than the first precision. The adder data path may include an adder of the second precision that combines the results from the floating-point adder with zero, with a general-purpose input, or with other dot product terms. Operated in this way, the specialized processing block provides a technical improvement of greatly increasing the functional density for implementing machine learning algorithms.

US Patent:

20210048984, Feb 18, 2021

Filed:

May 29, 2020

Appl. No.:

16/887784

Inventors:

- Palo Alto CA, US
Kevin Altair Hurd - Redwood City CA, US
Emil Talpes - San Mateo CA, US

International Classification:

G06F 7/575
G06T 1/20
G06F 15/80
G06F 7/52
G06F 7/50
G06N 3/063
G06N 3/04
G06F 7/544
G06F 17/16

Abstract:

Various embodiments of the disclosure relate to an accelerated mathematical engine. In certain embodiments, the accelerated mathematical engine is applied to image processing such that convolution of an image is accelerated by using a two-dimensional matrix processor comprising sub-circuits that include an ALU, output register and shadow register. This architecture supports a clocked, two-dimensional architecture in which image data and weights are multiplied in a synchronized manner to allow a large number of mathematical operations to be performed in parallel.

US Patent:

20200394095, Dec 17, 2020

Filed:

Mar 30, 2020

Appl. No.:

16/834104

Inventors:

- Palo Alto CA, US
Emil Talpes - San Mateo CA, US
Peter Bannon - Woodside CA, US
Kevin Hurd - Redwood City CA, US
Benjamin Floering - San Jose CA, US

International Classification:

G06F 11/07
G06N 3/02
G06F 11/32
G06F 11/30

Abstract:

A system for handling errors in a neural network includes a neural network processor for executing a neural network associated with use of a vehicle. The neural network processor includes an error detector configured to detect a data error associated with execution of the neural network and a neural network controller configured to receive a report of the data error from the error detector. In response to receiving the report, the neural network controller is further configured to signal that a pending result of the neural network is tainted without terminating execution of the neural network.

US Patent:

20200266705, Aug 20, 2020

Filed:

Nov 7, 2018

Appl. No.:

16/762481

Inventors:

- Palo Alto CA, US
Kevin Hurd - Redwood City CA, US
Satyan Chandra - Mountain View CA, US

International Classification:

H02M 3/156
G06F 1/20
G06F 1/26
H02M 1/12
H02M 7/00

Abstract:

A Voltage Regulator Module (VRM) includes a first voltage rail circuit board oriented in a first plane having formed therein a first plurality of conductors and configured to produce a first rail voltage, a second voltage rail circuit board oriented in a second plane that is substantially parallel to the first plane having formed therein a second plurality of conductors and configured to produce a second rail voltage. The VRM also includes a first capacitor circuit board oriented in a third plane that is (substantially perpendicular to the first plane and a second capacitor circuit board oriented in a fourth plane that is substantially parallel to the third plane. The VRM includes a plurality of conductors intercoupling the first voltage rail circuit board, the first capacitor circuit board, the second voltage rail circuit board, and the second capacitor circuit board.

US Patent:

20190250830, Aug 15, 2019

Filed:

Jun 5, 2018

Appl. No.:

16/000248

Inventors:

- Palo Alto CA, US
Kevin Altair HURD - Redwood City CA, US
Emil TALPES - San Mateo CA, US

Assignee:

Tesla, Inc. - Palo Alto CA

International Classification:

G06F 3/06
G06F 12/02

Abstract:

Presented are systems and methods that allow for efficient data processing that reduce data latency and, thus, power consumption and data management cost. In various embodiments, this is accomplished by using a sequencer that identifies an address pointer of a first data block within a memory and a length of data that comprises that data block and is related to an input of a matrix processor. The sequencer then calculates, based on the block length, the input length, and a memory map, a block count representative of a number of data blocks that are to be retrieved from the memory. Using the address pointer, the sequencer may retrieve a number of data blocks from the memory in a number of cycles that depends on whether the data blocks are contiguous. In embodiments, based on the length of data, a formatter then maps the data blocks to the input of the matrix processor.

US Patent:

20190205738, Jul 4, 2019

Filed:

Jan 4, 2018

Appl. No.:

15/862369

Inventors:

- Palo Alto CA, US
Kevin Altair Hurd - Redwood City CA, US

Assignee:

Tesla, Inc. - Palo Alto CA

International Classification:

G06N 3/063
G06K 9/66
G06F 15/18
G06K 9/34
G06K 9/46

Abstract:

Described herein are systems and methods that utilize a novel hardware-based pooling architecture to process the output of a convolution engine representing an output channel of a convolution layer in a convolutional neural network (CNN). The pooling system converts the output into a set of arrays and aligns them according to a pooling operation to generate a pooling result. In certain embodiments, this is accomplished by using an aligner that aligns, e.g., over a number of arithmetic cycles, an array of data in the output into rows and shifts the rows relative to each other. A pooler applies a pooling operation to a combination of a subset of data from each row to generate the pooling result.

Address:

PO Box 61646, Boulder City, NV 89006

Phone:

(702)5219206

VIN:

1YVHP80C975M15462

Make:

MAZDA

Model:

MAZDA6

Year:

2007