Kevin G Mclaughlin

US Patent:

7765128, Jul 27, 2010

Filed:

Jul 21, 2004

Appl. No.:

10/896287

Inventors:

Tyler Brooks - Seattle WA, US
Kevin McLaughlin - Charlestown MA, US
Helga Cecilia Dahl - Boston MA, US
Edward Kim - Seattle WA, US

Assignee:

Smart Destinations Inc. - Boston MA

International Classification:

G06Q 30/00

US Classification:

705 26

Abstract:

A smart-card based system and methods to control access to a plurality of attractions within a geographical area. The system may include one or more reward terminals that are located at attractions and are configured to read smart cards presented to them and, assuming the card is valid for that location, allow the card holder to access the attraction. Each smart card may be programmed with a product code that defines the attractions at which the card may be used. Product codes may be stored in a central database along with a list of the attractions associated with the each product code. The list of attractions may be updated as desired, thereby updating and changing the attractions at which any given card may be used.

US Patent:

8346618, Jan 1, 2013

Filed:

Jun 28, 2010

Appl. No.:

12/825183

Inventors:

Tyler Brooks - Seattle WA, US
Kevin McLaughlin - Charlestown MA, US
Helga Cecilia Dahl - Boston MA, US
Edward Kim - Seattle WA, US

Assignee:

Smart Destinations Inc. - Boston MA

International Classification:

G06Q 30/00
G06F 17/30

US Classification:

705 261, 705 271

Abstract:

A smart-card based system and methods to control access to a plurality of attractions within a geographical area. The system may include one or more reward terminals that are located at attractions and are configured to read smart cards presented to them and, assuming the card is valid for that location, allow the card holder to access the attraction. Each smart card may be programmed with a product code that defines the attractions at which the card may be used. Product codes may be stored in a central database along with a list of the attractions associated with the each product code. The list of attractions may be updated as desired, thereby updating and changing the attractions at which any given card may be used.

US Patent:

47852593, Nov 15, 1988

Filed:

Feb 1, 1988

Appl. No.:

7/150607

Inventors:

Walter C. Seelbach - Fountain Hills AZ
Kevin L. McLaughlin - Eau Claire WI
Danny J. Molezion - Norcross GA

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H03F 316
H03F 345

US Classification:

330300

Abstract:

A BIMOS amplifier having feedback clamping the amplifier's input to a predetermined voltage, minimizes input signal voltage excursions in the presence of large load capacitances. A pair of differentially coupled NPN transistors in response to first and second inputs drive a pair of emitter follower NPN transistors. First and second MOS transistors responsive to first and second enable signals are coupled between the ouptut from each of the emitters of the emitter follower transistors and the first and second inputs, respectively.

US Patent:

48574791, Aug 15, 1989

Filed:

May 9, 1988

Appl. No.:

7/191923

Inventors:

Kevin L. McLaughlin - Chandler AZ
Thomas P. Bushey - Phoenix AZ

Assignee:

Motorola - Schaumburg IL

International Classification:

H01L 2136
H01L 2138

US Classification:

437162

Abstract:

Improved semiconductor devices having minimum parasitic junction area are formed by using multiple buried polycrystalline conductor layers to make lateral contact to one or more pillar-shaped epitaxial single crystal device regions. The lateral poly contacts are isolated from each other and from the substrate and have at least one polycrystalline pillar extending to upper surface of the device to permit external connections to the lowest poly layer. The lateral epi-poly sidewall contacts are recessed under the intervening oxide layers to separate them from the active device regions in the center of the epi pillar. The structure is made by depositing three dielectric layers with two poly layers sandwiched in between. Holes are anisotropically etched to the lowest poly layer and the substrate. The exposed edges of the poly layers are oxidized.

US Patent:

45718172, Feb 25, 1986

Filed:

Mar 15, 1985

Appl. No.:

6/712041

Inventors:

Mark S. Birritella - Phoenix AZ
Kevin McLaughlin - Chandler AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 21225
H01L 21265
H01L 21308

US Classification:

29576B

Abstract:

A means and method is described for forming closely spaced contacts to adjacent semiconductor regions, such as the base and emitter of a bipolar transistor, so that the lateral voltage drops between the contacts and an intervening junction are minimized. The emitter and base and the contacts thereto are self-aligned. This is accomplished by a structure utilizing two poly-layers separated by one or more intermediate dielectric layers. The upper of the two poly-layers serves as a selective etching mask for defining the contact geometry and separation. The lower of the two poly-layers has one portion which becomes a poly-contact and diffusion source for the base region and a second portion which becomes a poly-contact and diffusion source for the emitter region. A single mask is used in connection with ion bombardment to alter the etch rate of portions of the poly-layers. This mask together with subsequent etch steps, defines the emitter width and location and the base-emitter contact separation.

US Patent:

46960970, Sep 29, 1987

Filed:

Oct 8, 1985

Appl. No.:

6/785414

Inventors:

Kevin L. McLaughlin - Chandler AZ
Thomas P. Bushey - Phoenix AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 21283
H01L 21302

US Classification:

437193

Abstract:

Improved semiconductor devices having minimum parasitic junction area are formed by using multiple buried polycrystalline conductor layers to make lateral contact to one or more pillar-shaped epitaxial single crystal device regions. The lateral poly contacts are isolated from each other and from the substrate and have at least one polycrystalline pillar extending to upper surface of the device to permit external connections to the lower poly layer. The structure is made by depositing three dielectric layers with two poly layers sandwiched in between. Holes are anisotropically etched to the lowest poly layer and the substrate. A conformal oxide is applied over the whole structure and anisotropically etched to remove the bottom portions in the hole where the poly pillar and the isolation wall are to be formed and isotropically where the single crystal pillar is to be formed. The remaining oxide regions isolate the buried conductor layers, contacts, and isolation walls. The polycrystalline pillar extending from the lowest poly layer to the device surface is formed at the same time as the epi-pillar.

US Patent:

46381864, Jan 20, 1987

Filed:

Dec 2, 1985

Appl. No.:

6/803691

Inventors:

Kevin L. McLaughlin - Chandler AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H03K 1901

US Classification:

307446

Abstract:

A BIMOS circuit is provided wherein an output terminal is coupled between upper and lower NPN push-pull transistors for providing high current drive capability along with no d. c. power dissipation. A first MOS transistor circuit is coupled between an input terminal and the lower transistor for biasing the lower transistor. A second MOS transistor circuit is coupled between the input terminal and the upper transistor for biasing the upper transistor. A third circuit is coupled between the input terminal and the lower transistor and is responsive to the output terminal for biasing the lower transistor.

US Patent:

46820540, Jul 21, 1987

Filed:

Jun 27, 1986

Appl. No.:

6/879750

Inventors:

Kevin L. McLaughlin - Chandler AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H03K 1901

US Classification:

307446

Abstract:

A BIMOS circuit is provided wherein an output terminal is coupled between an upper NPN and a lower PNP pair of push-pull transistors for providing high current drive capability along with no d. c. power dissipation. A P-channel MOS transistor is coupled between a node and both the collector of the NPN transistor and a first supply voltage terminal for biasing the NPN transistor. An N-channel MOS transistor is coupled between the node and both the collector of the PNP transistor and a second supply voltage terminal for biasing the PNP transistor. The gates of the MOS devices are connected to an input terminal. The node is further coupled to the bases of the NPN and PNP transistors and is coupled to the output terminal by a transmission gate or a resistor for increasing the output voltage swing.