Kevin S O'Connor

US Patent:

H97, Aug 5, 1986

Filed:

Dec 21, 1982

Appl. No.:

6/451786

Inventors:

Kevin J. O'Connor - Center Valley PA

Assignee:

AT&T Bell Laboratories - Murray Hill NJ

International Classification:

G11C 800

US Classification:

365230

Abstract:

A static noninverting driver circuit is used with a standard static address-row-decoder circuit in order to provide capacitance load drive capability and relatively high-speed operation. The driver circuit uses n-channel enhancement and depletion mode field effect transistors and a feedback bootstrap capacitor to achieve low power-high speed operation with a full VDD output high level.

US Patent:

7845985, Dec 7, 2010

Filed:

Dec 4, 2008

Appl. No.:

12/328577

Inventors:

David L. Brunker - Naperville IL, US
Timothy R. Gregori - Lockport IL, US
David E. Dunham - Aurora IL, US
Jason E. Squire - Batavia IL, US
Kevin O'Connor - Lisle IL, US
Joseph D. Comerci - Elmhurst IL, US

Assignee:

Molex Incorporated - Lisle IL

International Classification:

H01R 24/00

US Classification:

439631

Abstract:

A connector includes a housing with a set of broad-side coupled terminals configured to engage a pair of signal traces on a first panel and a second panel and transfer signals between the signal traces on the first and second panels. The connector may be slid onto the edges and then fastened to one or both of the panels with a locking feature. Multiple signal pairs may be included in the connector and may be electrically separated. The design of the connector helps facilitate high-speed data communication per signal pair with a return loss performance that does not exceed at predetermined level. Certain configurations of the connector may be used for co-planar configurations. Certain configurations of the connector may couple together panels of different thicknesses.

US Patent:

7976344, Jul 12, 2011

Filed:

Nov 9, 2010

Appl. No.:

12/942638

Inventors:

David L. Brunker - Naperville IL, US
Timothy R. Gregori - Lockport IL, US
David E. Dunham - Aurora IL, US
Jason E. Squire - Batavia IL, US
Kevin O'Connor - Lisle IL, US
Joseph D. Comerci - Elmhurst IL, US

Assignee:

Molex Incorporated - Lisle IL

International Classification:

H01R 24/00

US Classification:

439631

Abstract:

A connector includes a housing with a set of broad-side coupled terminals configured to engage a pair of signal traces on a first panel and a second panel and transfer signals between the signal traces on the first and second panels. The connector may be slid onto the edges and then fastened to one or both of the panels with a locking feature. Multiple signal pairs may be included in the connector and may be electrically separated. The design of the connector helps facilitate high-speed data communication per signal pair with a return loss performance that does not exceed at predetermined level. Certain configurations of the connector may be used for co-planar configurations. Certain configurations of the connector may couple together panels of different thicknesses.

US Patent:

7992294, Aug 9, 2011

Filed:

May 23, 2008

Appl. No.:

12/126635

Inventors:

Victor Zaderej - St. Charles IL, US
Kevin O'Connor - Lisle IL, US
Charlie Manlapaz - Brookfield IL, US
Timothy Hagan - Sugar Grove IL, US
Samuel C. Ramey - Naperville IL, US

Assignee:

Molex Incorporated - Lisle IL

International Classification:

H05K 3/02
H05K 3/10

US Classification:

29846, 29874, 29876

Abstract:

An interconnect device is used to mate a heat generating device to a power source. Plated components are provided on the interconnect device to provide a heat sink function for the heat generating device when the heat generating device is connected to the interconnect device, and to provide an electrical path between the heat generating device and the power source. A method of manufacturing same is also disclosed.

US Patent:

20080310167, Dec 18, 2008

Filed:

May 23, 2008

Appl. No.:

12/126657

Inventors:

VICTOR ZADEREJ - ST. CHARLES IL, US
KEVIN O'CONNOR - LISLE IL, US
CHARLIE MANLAPAZ - BROOKFIELD IL, US
TIMOTHY HAGAN - SUGAR GROVE IL, US
SAMUEL C. RAMEY - NAPERVILLE IL, US

International Classification:

F21V 29/00
H05K 7/20

US Classification:

362294, 361707

Abstract:

An interconnect device is used to mate a heat generating device to a power source. Plated components are provided on the interconnect device to provide a heat sink function for the heat generating device when the heat generating device is connected to the interconnect device, and to provide an electrical path between the heat generating device and the power source. A method of manufacturing same is also disclosed.

US Patent:

20120040565, Feb 16, 2012

Filed:

Feb 15, 2010

Appl. No.:

13/201719

Inventors:

Timothy R. Gregori - Lockport IL, US
Joseph D. Comerci - Elmhurst IL, US
Kevin O'Connor - Lisle IL, US
Herbert Endres - Munich, DE
Mikael Sigfridsson - Stockholm, SE

Assignee:

Molex Incorporated - Lisle IL

International Classification:

H01R 24/20

US Classification:

439660

Abstract:

A co-edge connector () is provided that includes a housing () that supports a plurality of terminals (). One side of the housing includes a slot () that is configured to accept a panel () and first terminal contacts () are positioned in the slot. An exposed support surface () extends from a wall () on a second side and second terminal contacts () extend above the support surface. In operation, if the panel inserted into the slot is inserted in a vertical direction, the second contacts can engage pads of panel where the panel is mounted on the housing by moving the panel in a vertical direction.

US Patent:

45688443, Feb 4, 1986

Filed:

Feb 17, 1983

Appl. No.:

6/467215

Inventors:

Kevin J. O'Connor - Center Valley PA

Assignee:

AT&T Bell Laboratories - Murray Hill NJ

International Classification:

H03K 19003
H03K 19094
H03K 1710

US Classification:

307475

Abstract:

A field effect transistor inverter-level shifter circuit which accepts TTL input level signals and generates MOS output level signals consists of the series combination of a load device, an enhancement mode transistor, and a depletion mode transistor. The gates of the enhancement and depletion mode transistors are connected to an input terminal. The source of the enhancement transistor is connected to the drain of the depletion transistor. The depletion transistor acts to control the potential of the source of the enhancement transistor so as to allow it to tolerate worse case TTL input potential "0" levels while not becoming more than only weakly biased on.

US Patent:

46601775, Apr 21, 1987

Filed:

Jan 14, 1985

Appl. No.:

6/691418

Inventors:

Kevin J. O'Connor - Center Valley PA

Assignee:

American Telephone and Telegraph Company - Murray Hill NJ
AT&T Bell Laboratories - Murray Hill NJ

International Classification:

G11C 1300

US Classification:

365189

Abstract:

A dual port memory is implemented in complementary (e. g. , CMOS) technology so as to allow simultaneous uncontested read operations to the same memory cell. This is achieved by accessing one node of a bistable static cell through a n-channel and a p-channel access transistor. The opposite node is typically left unconnected to external access means. This technique also reduces the area required to implement the memory cell as compared to prior art NMOS techniques. If desired, an arbitration circuit can be included to arbitrate between simultaneous read/read or read/write operations on the same cell from the two ports.