Khanh Tuan Tran

US Patent:

6455098, Sep 24, 2002

Filed:

Mar 8, 2001

Appl. No.:

09/802692

Inventors:

Khanh Tran - San Jose CA
Tom Kelly - Milipitas CA
Arin Chang - San Jose CA
Guy Mendez - Fremont CA

Assignee:

Semix Incorporated - Fremont CA

International Classification:

B05D 302

US Classification:

427 8, 42725518, 4272555, 427331, 427337, 427344, 427444

Abstract:

A method and apparatus are described for transferring processing structures between first and second processing environments. The apparatus includes a first apparatus compartment configured to provide the first processing environment and a second apparatus compartment configured to provide the second processing environment. The apparatus is preferably configured for transferring wafer structures between the processing environments. The first and second processing environments are coupled together through a transfer passage that is opened and closed in order to isolate the wafer in a small transfer volume between the processing environments. Preferably, the transfer passage is opened and closed with first and second movable tables to create the small volume transfer cavity. In operation, the wafer is isolated within the small volume transfer cavity and the first and second tables are individually raised and lowered to expose the wafer to the first and second processing environments without opening the transfer passage between the first and second apparatus compartments. According to an embodiment of the invention, the apparatus is configured with a chemical delivery system that monitors the chemical composition or chemical concentration within the second apparatus compartment and supplies the appropriate quantity of chemical or chemicals to maintain a selected composition or concentration therein.

US Patent:

6472751, Oct 29, 2002

Filed:

Sep 6, 2000

Appl. No.:

09/656437

Inventors:

Robert C. Chen - Los Altos CA
Jeffrey A. Shields - Sunnyvale CA
Robert Dawson - Austin TX
Khanh Tran - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2940

US Classification:

257758, 257759, 257760, 257774, 257700, 257787, 257649, 257751, 438687, 438688, 438689

Abstract:

A dielectric interlayer is formed over a semiconductor substrate comprising at least one active region. The exposed upper surface of the dielectric interlayer is treated with nitrogen to form a nitrided barrier layer thereon. At least one hydrogen-containing dielectric layer is formed over the dielectric interlayer having the nitrided barrier layer thereon. The nitrided barrier layer serves as a barrier to diffusion of hydrogen from the at least one hydrogen-containing dielectric layer into the dielectric interlayer, thereby preventing a decrease in hot carrier injection reliability.

US Patent:

6492258, Dec 10, 2002

Filed:

Jun 14, 2001

Appl. No.:

09/881831

Inventors:

Minh Van Ngo - Union City CA
Paul R. Besser - Sunnyvale CA
Matthew Buynoski - Palo Alto CA
John Caffall - San Carlos CA
Nick Maccrae - San Jose CA
Richard J. Huang - Cupertino CA
Khanh Tran - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 214763

US Classification:

438622, 438623, 438625, 438648, 438656, 438688, 257765, 257763, 257764

Abstract:

A method for making 0. 25-micron semiconductor chips includes annealing the metal interconnect lines prior to depositing an inter-layer dielectric (ILD) between the lines. During annealing, an alloy of aluminum and titanium forms, which subsequently volumetrically contracts, with the contraction being absorbed by the aluminum. Because the alloy is reacted prior to ILD deposition, however, the aluminum is not constrained by the ILD when it attempts to absorb the contraction of the alloy. Consequently, the likelihood of undesirable void formation. in the interconnect lines is reduced. The likelihood of undesirable void formation is still further reduced during the subsequent ILD gapfill deposition process by using relatively low bias power to reduce vapor deposition temperature. and by using relatively low source gas deposition flow rates to reduce flow-induced compressive stress on the interconnect lines during ILD formation.

US Patent:

6522013, Feb 18, 2003

Filed:

Aug 19, 1998

Appl. No.:

09/136527

Inventors:

Robert C Chen - Los Altos CA
Jeffrey A. Shields - Sunnyvale CA
Robert Dawson - Austin TX
Khanh Tran - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2348

US Classification:

257774, 257751, 257752, 257763

Abstract:

Punch-through vias are filled by initially depositing a thin, conformal layer of titanium nitride by chemical vapor deposition to cover an exposed upper surface of a lower metal feature, e. g. portions exposed by penetrating and undercutting an anti-reflective coating. A metal such as tungsten is subsequently deposited to fill the punch-through via. Embodiments include thermal decomposition of an organic-titanium compound, such as tetrakis-dimethylamino titanium, and treating the deposited titanium nitride in an H /N plasma to lower its resistivity. Moreover, the thickness of the anti-reflective coating can be reduced and the process window for etching the via widened.

US Patent:

6607962, Aug 19, 2003

Filed:

Aug 9, 2001

Appl. No.:

09/925945

Inventors:

Viktor Zekeriya - Atherton CA
Khanh Tran - Milpitas CA

Assignee:

Maxim Integrated Products, Inc. - Sunnyvale CA

International Classification:

H01L 2120

US Classification:

438384, 438382, 438597, 438672, 438675

Abstract:

A method of forming a thin film resistor contact incorporates an etch-stop material to protect the underlying thin film resistor from a subsequent dry etching process to form a contact opening to the thin film resistor. More specifically, the method includes forming a thin film resistor, forming a first dielectric layer over the thin film resistor, forming a first opening through the first dielectric layer to expose an underlying portion of the thin film resistor, forming an etch-stop within the first opening of the first dielectric layer, forming a second dielectric layer over the etch-stop and the first dielectric layer, forming a second opening through the second dielectric layer to expose the underlying portion of the etch-stop, and forming a metal plug within the second contact opening, wherein the metal plug is in electrical contact with the thin film resistor by way of the etch-stop. Alternatively, in the case of an insulating etch-stop, the second opening through the dielectric layer is through the etch-stop, and forming a metal plug within the second contact opening, wherein the metal plug is in direct electrical contact with the thin film resistor.

US Patent:

7664982, Feb 16, 2010

Filed:

Oct 26, 2006

Appl. No.:

11/588441

Inventors:

Lawton Chun-Hing Mue - Cupertino CA, US
Inderjit Singh Chohan - Cupertino CA, US
Khanh Tran - Cupertino CA, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 11/00

US Classification:

714 5, 714 6, 714 15, 711162

Abstract:

Methods and systems for storing recovery related information on a computer memory are described. One exemplary method comprises accessing a user input relating to a user selection of applications to be restored upon executing a recovery of the memory and storing on a recovery partition of the memory a recovery image corresponding to a user image on a user partition of the memory. The user image comprises the user selection of applications. Upon executing a recovery, the recovery image is copied to the user partition such that the user image is configured to correspond to the recovery image. The recovery image is derived from a set of applications that includes at least one un-installed application.

US Patent:

7921836, Apr 12, 2011

Filed:

May 7, 2009

Appl. No.:

12/436806

Inventors:

Khanh Tran - San Jose CA, US

Assignee:

Real Action Paintball, Inc. - San Jose CA

International Classification:

F41B 11/00

US Classification:

124 511, 124 49

Abstract:

A paintball marker includes a main body and a dual feed adapter coupled to the main body. The dual feed adapter has a hollow interior, a top feed port and a bottom feed port. A top feed storage hopper is detachably connected to the dual feed adapter at the top feed port, and a bottom feed storage magazine is detachably connected to the dual feed adapter at the bottom feed port. A sleeve with an opening is rotatable within the dual feed adapter between a first position where the sleeve opening aligns with the top feed port for feeding therethrough a first group of paintballs from the hopper, and a second position where the sleeve opening aligns with the bottom feed port for feeding therethrough a second group of paintballs from the magazine.

US Patent:

7943473, May 17, 2011

Filed:

Jan 13, 2009

Appl. No.:

12/352679

Inventors:

Joseph Paul Ellul - San Jose CA, US
Khanh Tran - Milpitas CA, US
Albert Bergemont - Palo Alto CA, US

Assignee:

Maxim Integrated Products, Inc. - Sunnyvale CA

International Classification:

H01L 21/20

US Classification:

438386, 438381

Abstract:

Passive, high density, 3d IC capacitor stacks and methods that provide the integration of capacitors and integrated circuits in a wafer to wafer bonding process that provides for the integration of capacitors formed on one wafer, alone or with active devices, with one or more integrated circuits on one or more additional wafers that may be stacked in accordance with the process. Wafer to wafer bonding is preferably by thermo-compression, with grinding and chemical mechanical polishing being used to simply aspects of the process of fabrication. Various features and alternate embodiments are disclosed.