Ki Hyung Lee

Address:

510 S Ardmore Ave APT 233, Los Angeles, CA 90020

Phone:

(213)8205039

VIN:

WDDHF5KBXCA564871

Make:

MERCEDES-BENZ

Model:

E-CLASS

Year:

2012

Address:

510 S Ardmore Ave, Los Angeles, CA 90020

Phone:

(213)8205039

VIN:

WMWSV3C54BTY14525

Make:

MINI

Model:

COOPER

Year:

2011

US Patent:

56688300, Sep 16, 1997

Filed:

May 3, 1996

Appl. No.:

8/642570

Inventors:

Christos John Georgiou - White Plains NY
Thor Arne Larsen - Hopewell Junction NY
Ki Won Lee - Yorktown Heights NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H04L 2534

US Classification:

375220

Abstract:

A synchronizer and phase aligning method that provide signal smoothing and filtering functions as well as slip-cycle compensation, and allow for multichannel digital phase alignment, bus deskewing, integration of multiple transceivers within a single semiconductor chip, etc. A delay line produces a plurality of delayed input replicas of an input signal. A clock phase adjuster produces a sampling clock signal from a reference clock signal. The sampling clock signal may be phase adjusted to be offset from the input signal. After certain smoothing and filtering functions, selection logic detects a phase relationship between the sampling clock signal and the input replicas and identifies a closely synchronized signal for output. Using this identified replica signal, slip-cycle compensation and retiming logic outputs a compensated data output signal synchronized with the reference clock signal. Also, an integrated multiple transceiver produced using the phase alignment technique is presented.

US Patent:

55508600, Aug 27, 1996

Filed:

Apr 11, 1995

Appl. No.:

8/420102

Inventors:

Christos J. Georgiou - White Plains NY
Thor A. Larsen - Hopewell Junction NY
Ki W. Lee - Yorktown Heights NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H04L 2534

US Classification:

375220

Abstract:

A synchronizer and phase aligning method that provide signal smoothing and filtering functions as well as slip-cycle compensation, and allow for multichannel digital phase alignment, bus deskewing, integration of multiple transceivers within a single semiconductor chip, etc. A delay line produces a plurality of delayed input replicas of an input signal. A clock phase adjuster produces a sampling clock signal from a reference clock signal. The sampling clock signal may be phase adjusted to be offset from the input signal. After certain smoothing and filtering functions, selection logic detects a phase relationship between the sampling clock signal and the input replicas and identifies a closely synchronized signal for output. Using this identified replica signal, slip-cycle compensation and retiming logic outputs a compensated data output signal synchronized with the reference clock signal. Also, an integrated multiple transceiver produced using the phase alignment technique is presented.

US Patent:

55330720, Jul 2, 1996

Filed:

Nov 12, 1993

Appl. No.:

8/152108

Inventors:

Christos J. Georgiou - White Plains NY
Thor A. Larsen - Hopewell Junction NY
Ki W. Lee - Yorktown Heights NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03D 324

US Classification:

375371

Abstract:

A synchronizer and phase aligning method that provide signal smoothing and filtering functions as well as slip-cycle compensation, and allow for multichannel digital phase alignment, bus deskewing, integration of multiple transceivers within a single semiconductor chip, etc. A delay line produces a plurality of delayed input replicas of an input signal. A clock phase adjuster produces a sampling clock signal from a reference clock signal. The sampling clock signal may be phase adjusted to be offset from the input signal. After certain smoothing and filtering functions, selection logic detects a phase relationship between the sampling clock signal and the input replicas and identifies a closely synchronized signal for output. Using this identified replica signal, slip-cycle compensation and retiming logic outputs a compensated data output signal synchronized with the reference clock signal. Also, an integrated multiple transceiver produced using the phase alignment technique is presented.

US Patent:

20220310530, Sep 29, 2022

Filed:

Mar 22, 2022

Appl. No.:

17/655801

Inventors:

- Irvine CA, US
Hoang Mong Nguyen - Fountain Valley CA, US
Matthew Sean Read - Foothill Ranch CA, US
Howard E. Chen - Anaheim CA, US
Ki Wook Lee - Irvine CA, US
Yi Liu - San Diego CA, US

International Classification:

H01L 23/552
H01L 23/31
H01L 25/065
H01L 23/498
H01L 21/56
H01L 21/48
H01L 25/00

Abstract:

A packaged semiconductor module comprises a substrate having a ground plane, an electronic device mounted on a surface of the substrate, a bond pad disposed on the surface of the substrate and electrically connected to the ground plane, a mold compound covering the electronic device, a conductive post disposed on a side of the electronic device, the conductive post extending from the bond pad and at least partially through the mold compound, and a conductive layer disposed on the mold compound and electrically coupled to the conductive post and to the ground plane, the conductive post, the conductive layer, and the ground plane together forming the integrated electromagnetic interference shield, the conductive post extending from the bond pad to the conductive layer in a direction perpendicular to a plane defined by the surface of the substrate.

US Patent:

20230115846, Apr 13, 2023

Filed:

Oct 19, 2021

Appl. No.:

17/504911

Inventors:

- Irvine CA, US
Anthony James LoBianco - Irvine CA, US
Howard E. Chen - Anaheim CA, US
Ki Wook Lee - Irvine CA, US
Yi Liu - San Diego CA, US

International Classification:

H01L 23/498
H01L 21/56
H01L 21/48
H01L 23/31
H01L 25/10
H01L 25/00

Abstract:

An electronic package is provided. The electronic package comprises a substrate having a first side and a second side, the substrate configured to receive one or more electronic components; a first electronic component mounted to the first side of the substrate; a first mold structure extending over at least part of the first side of the substrate; a group of through-mold connections provided on the first side of the substrate, the through-mold connections substantially formed of non-reflowable electrically conductive material; the first mold structure substantially encapsulating the group of through-mold connections; the group of through-mold connections exposed through the first mold structure. An electronic device comprising such an electronic package is also provided. A method of manufacturing such an electronic package is also provided.

US Patent:

20230016601, Jan 19, 2023

Filed:

Jul 13, 2022

Appl. No.:

17/863959

Inventors:

- Hackensack NJ, US
Ki S. LEE - Palisades Park NJ, US

International Classification:

F21V 3/00
H05B 45/18

Abstract:

An LED specification system is provided having at least one LED light output device. The LED light output device has an LED light source, a first exchangeable face panel selectable from a plurality of potential exchangeable face panels, and a housing for locating the exchangeable face panel relative to the LED light source and for orienting the LED light source such that light from the LED light source passes through the first exchangeable face panel. The LED specification system further includes a user interface for selecting at least one preferred output characteristic for light from the LED light output device. The preferred output characteristic is defined by a metric value. The LED specification system further includes a transformation module for defining an LED specification value based at least partially on the defined metric value and a characteristic of the LED light source.

US Patent:

20210315109, Oct 7, 2021

Filed:

Apr 14, 2021

Appl. No.:

17/230367

Inventors:

- Irvine CA, US
Ki Wook Lee - Irvine CA, US

International Classification:

H05K 3/46
H01Q 1/38
H05K 1/16

Abstract:

A method of making a printed circuit board structure including a closed cavity is provided. The method can include the steps of forming a cavity in a core structure of a core layer, laminating each of a top surface and a bottom surface of the core structure with an adhesive layer and a metal layer to prepare a laminate structure and cover the cavity to define a closed cavity. The method also includes forming vias through the laminate structure, and patterning the metal layers in the laminate structure.

US Patent:

20210315110, Oct 7, 2021

Filed:

Apr 14, 2021

Appl. No.:

17/230584

Inventors:

- Irvine CA, US
Ki Wook Lee - Irvine CA, US

International Classification:

H05K 3/46
H01Q 1/38
H05K 1/16

Abstract:

A method of making a printed circuit board structure including a closed cavity is provided. The method can include the steps of forming a cavity in a core structure of a core layer, laminating each of a top surface and a bottom surface of the core structure with an adhesive layer and a metal layer to prepare a laminate structure and cover the cavity to define a closed cavity. The method also includes forming vias through the laminate structure, and patterning the metal layers in the laminate structure.