Kim Chin Chen

US Patent:

6698646, Mar 2, 2004

Filed:

Sep 11, 2002

Appl. No.:

10/241495

Inventors:

Kim H Chen - Fremont CA
Soojin Choi - Santa Clara CA
Chun Yee Chan - Singapore, SG
Johnny Monis Nigos - Singapore, SG

Assignee:

Agilent Technologies, Inc. - Palo Alto CA

International Classification:

B23K 106

US Classification:

2281805

Abstract:

The present invention is a method for bonding gold wire to gold bond pads at temperatures lower than 125 degrees Celsius, and more particularly at room temperature, defined to be 25 degrees Celsius. By applying compressive force and ultrasonic energy, an intermetallic bond can be formed between a gold wire and a gold bond pad without elevating the temperature. Furthermore, the present invention uses ultrasonic energy with frequencies low enough to be in the range of commercially available wire bonders.

US Patent:

6907459, Jun 14, 2005

Filed:

Mar 30, 2001

Appl. No.:

09/820706

Inventors:

Ed H. Chi - Palo Alto CA, US
Kim K Chen - Dunwoody GA, US

Assignee:

Xerox Corporation - Stamford CT

International Classification:

G06F015/173

US Classification:

709224, 7155011, 707 3, 707 5

Abstract:

Techniques are provided for predicting the usage of a document collection given proximal cue information in the documents, a starting point and the user's information needs. A document collection topology matrix is created indicating links between document content portions. The link entry documents are analyzed for proximal cue words based on link URL, surrounding text and title. For image links, the connected to document information may also be used. Proximal cue words are added to a matrix relating proximal cue words and links. The proximal scent matrix indicates a similarity between the user's information need and the proximal cue word matrix. A distal scent information matrix is also calculated using distal document information and combined with the proximal scent matrix. Spreading activation is then applied to the resulting matrix using the starting location for a requested number of iterations and resulting in a predicted usage of the document collection.

US Patent:

7514775, Apr 7, 2009

Filed:

Oct 9, 2006

Appl. No.:

11/539814

Inventors:

Clinton Chao - Hsinchu, TW
Tsorng-Dih Yuan - Hsinchu, TW
Hsin-Yu Pan - Taipei, TW
Kim Chen - Fremont CA, US
Mark Shane Peng - Hsinchu, TW
Tjandra Winata Karta - Hsinchu, TW

Assignee:

Taiwan Semiconductor Manufacturing Co., Ltd. - Hsin-Chu

International Classification:

H01L 23/498

US Classification:

257686, 257698, 257706, 257777, 257E23063

Abstract:

A stacked structure includes a first die coupled to a first substrate and having a first conductive structure formed through the first die. A second die is mounted over the first die. The second die is coupled to the first substrate by the first conductive structure. At least one first support structure formed from a second substrate is provided over the first substrate, adjacent to at least one of the first die and the second die. A top surface of the first support structure is substantially coplanar with a top surface of at least one of the first and second dies adjacent to the first support structure. The stacked structure further includes a heat spreader mounted over the second die.

US Patent:

7565635, Jul 21, 2009

Filed:

Apr 9, 2007

Appl. No.:

11/697744

Inventors:

Clinton Chao - Hsinchu, TW
Louis Liu - Hsin-Chu, TW
Lewis Chu - Pingjhen, TW
Mark Shane Peng - Hsinchu, TW
Chao-Shun Hsu - Sansing Township, Yilan County, TW
Kim Chen - Fremont CA, US

Assignee:

Taiwan Semiconductor Manufacturing Co., Ltd. - Hsin-Chu

International Classification:

G06F 17/50
G06F 9/45

US Classification:

716 5, 716 4, 716 7, 716 16

Abstract:

SiP design systems and methods. The system comprises a system partitioning module, a subsystem integration module, a physical design module, and an analysis module. The system partitioning module partitions a target system into subsystem partitions according to partition criteria. The subsystem integration module generates an architecture design and/or a cost estimation for the target system according to the subsystem partitions, at least one SiP platform, and IC geometry data. The physical design module generates a SiP physical design with physical routing for the target system according to the architecture design, the subsystem partitions, the SiP platform, and the IC geometry data. The analysis module performs a performance check within the subsystem partitions based on the SiP physical design and/or simulations of the target system.

US Patent:

8519537, Aug 27, 2013

Filed:

Jun 10, 2010

Appl. No.:

12/813212

Inventors:

Shin-Puu Jeng - Hsin-Chu, TW
Kim Hong Chen - Fremont CA, US
Shang-Yun Hou - Hsin-Chu, TW
Chao-Wen Shih - Zhubei, TW
Cheng-Chieh Hsieh - Yongkang, TW
Chen-Hua Yu - Hsin-Chu, TW

Assignee:

Taiwan Semiconductor Manufacturing Company, Ltd. - Hsin-Chu

International Classification:

H01L 23/13
H01L 23/538
H01L 23/488

US Classification:

257738, 257E23023, 257E21509, 257E23173, 257777, 257737, 257686, 257685, 257723, 257773, 257774, 257668, 257727, 257728, 257778

Abstract:

A 3D semiconductor package using an interposer is provided. In an embodiment, an interposer is provided having a first die electrically coupled to a first side of the interposer and a second die electrically coupled to a second side of the interposer. The interposer is electrically coupled to an underlying substrate, such as a packaging substrate, a high-density interconnect, a printed circuit board, or the like. The substrate has a cavity such that the second die is positioned within the cavity. The use of a cavity may allow smaller conductive bumps to be used, thereby allowing a higher number of conductive bumps to be used. A heat sink may be placed within the cavity to aid in the dissipation of the heat from the second die.

US Patent:

20030006267, Jan 9, 2003

Filed:

Jun 14, 2001

Appl. No.:

09/882135

Inventors:

Kim Chen - Fremont CA, US
Soojin Choi - Santa Clara CA, US
Chun Chan - Singapore, SG
Johnny Nigos - Singapore, SG

International Classification:

B23K001/06
B23K020/10
B23K031/02

US Classification:

228/110100, 228/180500, 228/001100, 228/004500

Abstract:

The present invention is a method for bonding gold wire to gold bond pads at temperatures lower than 125 degrees Celsius, and more particularly at room temperature, defined to be 25 degrees Celsius. By applying compressive force and ultrasonic energy, an intermetallic bond can be formed between a gold wire and a gold bond pad without elevating the temperature. Furthermore, the present invention uses ultrasonic energy with frequencies low enough to be in the range of commercially available wire bonders.

US Patent:

20080018350, Jan 24, 2008

Filed:

Sep 22, 2006

Appl. No.:

11/525581

Inventors:

Clinton Chao - Hsinchu, TW
Chih-Hsien Chang - Taipei, TW
John C.Y. Chiang - Hsin-Chu, TW
Mark Shane Peng - Hsinchu City, TW
Hua-Shu Wu - Hsinchu, TW
Kim Chen - Fremont CA, US
Wen-Hung Wu - Hsinchu City, TW
Tjandra Winada Karta - Hsinchu, TW

International Classification:

G01R 31/02

US Classification:

324754

Abstract:

An interposer for converting pitches includes an interconnect structure over the semiconductor substrate, an active circuit formed on the semiconductor substrate, wherein the active circuit is electrically connected to the interconnect structure, a first plurality of pads with a first pitch over the interconnect structure, a second plurality of pads underlying the semiconductor substrate, and a plurality of through-substrate vias in the semiconductor substrate, wherein the first and the second plurality of pads are interconnected through the plurality of through-substrate vias.

US Patent:

20130120018, May 16, 2013

Filed:

Nov 16, 2011

Appl. No.:

13/297779

Inventors:

Shang-Yun Hou - Hsin-Chu, TW
Wei-Cheng Wu - Hsin-Chu, TW
Hsien-Pin Hu - Zhubei City, TW
Jung Cheng Ko - Taichung City, TW
Shin-Puu Jeng - Hsin-Chu, TW
Chen-Hua Yu - Hsin-Chu, TW
Kim Hong Chen - Fremont CA, US

Assignee:

Taiwan Semiconductor Manufacturing Company, Ltd. - Hsin-Chu

International Classification:

G01R 31/26
H01L 23/48
H01L 21/58

US Classification:

32476201, 438107, 257737, 257E23011, 257E21505

Abstract:

A method and apparatus for testing the electrical characteristics, such as electrical continuity, is provided. A substrate, such as a wafer or an interposer, having a plurality of through vias (TVs) is provided. Along one side of the substrate, a conductive layer electrically couples two or more of the TVs. Thereafter, the electrical characteristics of the TVs may be test by, for example, a probe card in electrical contact with the TVs on the other side of the substrate. During testing, current passes through a first TV from a first side of the substrate, to the conductive layer on a second side of the substrate, to a second TV, and back to the first side of the substrate through the second TV.