Klaus J Ruff

US Patent:

7036053, Apr 25, 2006

Filed:

Dec 19, 2002

Appl. No.:

10/324864

Inventors:

John F. Zumkehr - Orange CA, US
John L. Bryan - Beaverton OR, US
Howard S. David - Portland OR, US
Klaus Ruff - Beaverton OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G01R 31/3183

US Classification:

714709, 714719, 714721, 714744

Abstract:

A method for optimizing a source synchronous clock reference signal timing to capture data from a memory device (e. g. , DDR SDRAM) includes conducting an iterative two-dimensional data eye search for optimizing the delay of the source synchronous clock reference signal (e. g. , DQS). Embodiments of the present invention are directed to tuning the delay for each device for the optimal margin in two dimensions: maximize the distance from the data eye walls and maximize the noise margin on the interface. An iterative data eye search is performed while varying the DQS delay timing and noise margin.

US Patent:

7246022, Jul 17, 2007

Filed:

Jun 20, 2005

Appl. No.:

11/156837

Inventors:

James A. McCall - Beaverton OR, US
Klaus Ruff - Beaverton OR, US
David Shykind - Sherwood OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G01K 1/20

US Classification:

702 99, 324105, 331 70, 331176, 331177 R, 331187, 368202, 700 71, 700299, 702 85, 702132

Abstract:

A method includes detecting a change in temperature in an integrated circuit that is coupled to a differential communication link, and responding to the detected change in temperature by initiating a retraining process for the differential communication link.

US Patent:

8578086, Nov 5, 2013

Filed:

Sep 25, 2009

Appl. No.:

12/567585

Inventors:

Santanu Chaudhuri - Mountain View CA, US
Klaus Ruff - Beaverton OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 12/00

US Classification:

711105, 711100, 711154, 711155

Abstract:

Link initialization techniques to decouple the read training from the write training. Read training may be accomplished in a robust manner before write training is performed. These techniques may provide significantly improved link initialization times. A user-programmable register within a dynamic random access memory (DRAM) module may be utilized by the decoupled read training and write training processes. The decoupling may result in shorter and more robust training segments that may support faster training and/or increased link speeds.

US Patent:

20060067398, Mar 30, 2006

Filed:

Sep 30, 2004

Appl. No.:

10/956426

Inventors:

James McCall - Beaverton OR, US
Klaus Ruff - Beaverton OR, US
David Shykind - Sherwood OR, US
Santanu Chaudhuri - Mountain View CA, US

International Classification:

H03K 5/159

US Classification:

375232000

Abstract:

A method, system and apparatus to self-determine equalization parameters for a channel. An initiator sends an equalization insensitive signal (EIS) to a responder on channel to be equalized and begins a count. A responder responds with an EIS. When the initiator receives the response EIS the count is terminated. The count, which constitutes a measure of delay in the channel, may be used to determine desirable equalization parameters for the channel.

US Patent:

62046845, Mar 20, 2001

Filed:

Nov 3, 1999

Appl. No.:

9/432357

Inventors:

Klaus Ruff - Beaverton OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03K 1716

US Classification:

326 30

Abstract:

A method of controlling a slew rate includes applying a resistive load to a bus corresponding to the number of logic components in a computer. The number of logic components within the computer is varied by either adding or removing a logic component. A second resistive load is selected to be applied to the bus after the number of logic circuits in the computer has been changed. The selection of a second resistance enables the slew rate to be controlled when the number of components change.

US Patent:

6028451, Feb 22, 2000

Filed:

Dec 31, 1997

Appl. No.:

9/001256

Inventors:

Klaus Ruff - Beaverton OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03K 190175

US Classification:

326 82

Abstract:

A slew rate control circuit of a bus includes two connection devices that are adapted to be coupled to two voltage supplies. The connection devices are connected to the bus by a select terminal of a signal application device. The signal application device has first and second positions which apply first and second amounts of resistance to the bus depending on the voltage on the select terminal. If an expansion board is adapted to be coupled to the bus, a different voltage is applied on the select terminal. A method for controlling a slew rate includes applying a resistive load to a bus corresponding to the number of logic circuits in a computer system. The number of logic circuits within the computer is varied by either adding or removing a logic circuit. A second resistive load is selected to be applied to the bus after the number of logic circuits in the computer system has been varied. The selection of a second resistance enables the amount of slew rate to be reduced.

US Patent:

20160379690, Dec 29, 2016

Filed:

Aug 1, 2016

Appl. No.:

15/225717

Inventors:

- Santa Clara CA, US
Klaus RUFF - Beaverton OR, US
George VERGIS - Portland OR, US
Suneeta SAH - Portland OR, US

International Classification:

G11C 7/10

Abstract:

A register not connected to a data bus is read by transferring data across an address bus to a device connected to the data bus, from which the data is read by a device connected to the data bus. The register resides in a register device connected via the address bus to a memory device that is connected to both the address bus and the data bus. A host processor triggers the register device to transfer information over the address bus to a register on the memory device. The host processor then reads the information from the register of the memory device.

US Patent:

20150089111, Mar 26, 2015

Filed:

Dec 4, 2014

Appl. No.:

14/560976

Inventors:

- Santa Clara CA, US
Klaus J. Ruff - Beaverton OR, US
George Vergis - Portland OR, US
Suneeta Sah - Portland OR, US

International Classification:

G06F 13/28
G06F 13/16

US Classification:

710306

Abstract:

A register not connected to a data bus is read by transferring data across an address bus to a device connected to the data bus, from which the data is read by a device connected to the data bus. The register resides in a register device connected via the address bus to a memory device that is connected to both the address bus and the data bus. A host processor triggers the register device to transfer information over the address bus to a register on the memory device. The host processor then reads the information from the register of the memory device.