Kok Lee

US Patent:

20150089462, Mar 26, 2015

Filed:

Dec 2, 2014

Appl. No.:

14/557920

Inventors:

- Mountain View CA, US
Sanjay Dhar - Lake Oswego OR, US
Vishal Khandelwal - Portland OR, US
Kok Kiong Lee - Sunnyvale CA, US

International Classification:

G06F 17/50

US Classification:

716105

Abstract:

Systems and techniques are described for performing circuit synthesis. Some embodiments create a lookup table based on information contained in a cell library. The lookup table is then used during circuit synthesis. Specifically, some embodiments optimize cells in a reverse-levelized cell ordering. For a given cell, a table lookup is performed to obtain a set of optimal cell configurations, and the cell is replaced with a cell configuration selected from the set of optimal cell configurations. Some embodiments concurrently optimize cells for timing, area, and power leakage based on the timing criticality of the cells.

US Patent:

20140237437, Aug 21, 2014

Filed:

Oct 31, 2013

Appl. No.:

14/068253

Inventors:

- Mountain View CA, US
Sanjay Dhar - Lake Oswego OR, US
Vishal Khandelwal - Portland OR, US
Kok Kiong Lee - Sunnyvale CA, US

Assignee:

Synopsys, Inc. - Mountain View CA

International Classification:

G06F 17/50

US Classification:

716104

Abstract:

Systems and techniques are described for performing circuit synthesis. Some embodiments create a lookup table based on information contained in a cell library. The lookup table is then used during circuit synthesis. Specifically, some embodiments optimize cells in a reverse-levelized cell ordering. For a given cell, a table lookup is performed to obtain a set of optimal cell configurations, and the cell is replaced with a cell configuration selected from the set of optimal cell configurations. Some embodiments concurrently optimize cells for timing, area, and power leakage based on the timing criticality of the cells.

US Patent:

20140181765, Jun 26, 2014

Filed:

Dec 23, 2013

Appl. No.:

14/139590

Inventors:

- Mountain View CA, US
Kok Kiong Lee - Sunnyvale CA, US
Sanjay V. Kumar - Fremont CA, US
Prashant Saxena - Portland OR, US
Robert L. Walker - Boulder CO, US

Assignee:

Synopsys, Inc. - Mountain View CA

International Classification:

G06F 17/50

US Classification:

716104

Abstract:

Systems and techniques are described for performing buffer tree synthesis. Some embodiments create a lookup table based on information contained in a cell library. The lookup table is then used during buffer tree synthesis.