Krishna B Rajan

US Patent:

7779316, Aug 17, 2010

Filed:

Dec 5, 2007

Appl. No.:

11/950578

Inventors:

Ishwardutt Parulkar - San Francisco CA, US
Gaurav H. Agarwal - Santa Clara CA, US
Krishna B. Rajan - Fremont CA, US
Paul J. Dickinson - San Jose CA, US

Assignee:

Oracle America, Inc. - Redwood City CA

International Classification:

G11C 29/00

US Classification:

714719, 714718, 714733, 714 30, 714 42, 714726, 714727, 714729, 36523003, 365200, 365154, 365201

Abstract:

A method and system for testing a chip at functional (operational) speed. The chip may include an integrated circuit having a number flops and memory arrays arranged into logically functioning elements. Additional flops may be included to output to one or more of the other flops in order to provide inputs to the flops at the functional speed such that the receiving flops executing at the functional speed according to the received input at a next functional clock pulse to facilitate testing the chip at the functional speed.

US Patent:

7797594, Sep 14, 2010

Filed:

Jul 5, 2007

Appl. No.:

11/773543

Inventors:

Ishwardutt Parulkar - San Francisco CA, US
Sriram Anandakumar - Sunnyvale CA, US
Krishna B. Rajan - Fremont CA, US

Assignee:

Oracle America, Inc. - Redwood City CA

International Classification:

G11C 29/00
G01R 31/28

US Classification:

714719, 714733

Abstract:

A method and apparatus for testing a three dimensional (3D) memory including a static array and an active array. The method is performed by a memory built-in self-test (MBIST) controller, and includes writing data to the static array, transferring data from the static array to the active array, and reading data from the active array. The method further includes, in a plurality of subsequent cycles, writing data to the static array; transferring data from static array to the active array, and reading data from the active array, wherein said writing data for each subsequent cycle is performed concurrently with reading data for a previous cycle.

US Patent:

20030149926, Aug 7, 2003

Filed:

Feb 7, 2002

Appl. No.:

10/072342

Inventors:

Krishna Rajan - Newark CA, US

International Classification:

G01R031/28

US Classification:

714/726000

Abstract:

Disclosed are novel methods and apparatus for efficiently providing a single scan chain design for hierarchically BISTed designs. In an embodiment, a method of providing a single scan chain of a chip is disclosed. The method includes: selecting a TOP chain of the chip, the chip being divided into a plurality of embedded logic test (ELT) blocks; bypassing periphery flops of the plurality of ELT blocks; selecting a single scan chain of all ELT blocks of the chip; and inserting the single scan chain of all ELT blocks of the chip into the TOP chain of the chip.

US Patent:

20030188243, Oct 2, 2003

Filed:

Mar 29, 2002

Appl. No.:

10/113365

Inventors:

Krishna Rajan - Newark CA, US

International Classification:

G01R031/28

US Classification:

714/731000

Abstract:

A TAP-controlled scan architecture is modified to include an additional pin to receive a double capture mode (DCM) signal that may be used to override a functional mode signal provided by a TAP controller to enable an externally generated functional clock to provide double capture clock pulses to an internal scan chain during testing without transitioning the TAP controller between states.