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Kuriappan P Alappat

age ~75

from Portland, OR

Also known as:
  • Kuriappan Paul Alappat
  • Paul K Alappat
  • Tessy Alappat
  • Kuriappan Lappat
  • Kuriappan T
  • P Alappat
  • Kuriappan I
Phone and address:
15173 Channa Dr, Portland, OR 97229
(503)6457004

Kuriappan Alappat Phones & Addresses

  • 15173 Channa Dr, Portland, OR 97229 • (503)6457004
  • Beaverton, OR

Work

  • Position:
    Professional/Technical

Education

  • Degree:
    Graduate or professional degree

Emails

Us Patents

  • Incremental Bus Structure For Modular Electronic Equipment

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  • US Patent:
    6629181, Sep 30, 2003
  • Filed:
    Mar 16, 2000
  • Appl. No.:
    09/527942
  • Inventors:
    Kuriappan P. Alappat - Portland OR
  • Assignee:
    Tektronix, Inc. - Beaverton OR
  • International Classification:
    G06F 1300
  • US Classification:
    710300, 439 55
  • Abstract:
    An incremental bus structure for a modular measurement instrument includes interface connector structural elements interconnecting segments of a system bus. The system bus contains electrically conductive lines with the system bus having at least one subset of N electrically conductive lines. Each interface connector is part of a measurement module and has at least one set of N electrically conductive input and output contacts corresponding with the N electrically conductive lines. The first input contact of the set of N contacts for each connector is coupled to an electronic element associated with its measurement module and the second and subsequent input contacts are connected to the first and subsequent output contacts.
  • Diode Fault Detection System And Method

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  • US Patent:
    6876102, Apr 5, 2005
  • Filed:
    Jul 24, 2002
  • Appl. No.:
    10/205140
  • Inventors:
    Kuriappan P. Alappat - Portland OR, US
  • Assignee:
    Intel Corporation - Santa Clara CA
  • International Classification:
    H02J001/10
  • US Classification:
    307 18
  • Abstract:
    Disclosed are a system and method of detecting a diode fault among diodes coupled to a plurality of redundant power feeds. A diode short fault may be detected by measuring a first voltage across a first one of the diodes, measuring a second voltage between two nodes including a terminal of the first diode and detecting the diode short based upon the first and second voltages. A diode open fault may be detected by decoupling a first one of the diodes from a power feed and measuring the voltage across the diode.
  • Method And Apparatus To Manage Airflow In A Chassis

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  • US Patent:
    7152418, Dec 26, 2006
  • Filed:
    Jul 6, 2004
  • Appl. No.:
    10/885181
  • Inventors:
    Kuriappan P. Alappat - Portland OR, US
    Brian S. Jarrett - Hillsboro OR, US
  • Assignee:
    Intel Corporation - Santa Clara CA
  • International Classification:
    F25D 17/04
    F25D 23/12
    F24F 7/00
    H05K 7/20
  • US Classification:
    62186, 622592, 236 493, 361690, 361695
  • Abstract:
    A method and apparatus to manage airflow in a chassis includes one or more airflow restrictor assemblies disposed adjacent a slot within the chassis. The airflow restrictor assemblies can be set in a plurality of positions between a minimum airflow position and a maximum airflow position. The position of the airflow restrictor assembly can be set in accordance with characteristics of the module inserted in the slot. The module characteristics may include power dissipation and airflow resistance.
  • Method For Dynamic Assignment Of Slot-Dependent Static Port Addresses

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  • US Patent:
    7340538, Mar 4, 2008
  • Filed:
    Dec 3, 2003
  • Appl. No.:
    10/727277
  • Inventors:
    Kuriappan P. Alappat - Portland OR, US
    Chetan Hiremath - Hillsboro OR, US
  • Assignee:
    Intel Corporation - Santa Clara CA
  • International Classification:
    G06F 3/00
    G06F 5/00
  • US Classification:
    710 5, 710 6, 710 41, 709224, 709226, 718104
  • Abstract:
    A method for dynamic assignment of slot-dependent static network port addresses. Under the method, a slot address and shelf address are determined for a card modular platform board installed in a given slot in a shelf. The slot and shelf addresses are used as inputs to return a unique network address. The unique network address is then assigned as a static network address for the board's network port. The unique address may be provided by an address proxy, including a boot server. Firmware and/or software stored on a board may also be employed to obtain the static network address. The address may be obtained from a pre-configured lookup table, or dynamically determined using an algorithm.
  • Backplane For Switch Fabric

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  • US Patent:
    7453870, Nov 18, 2008
  • Filed:
    Jun 12, 2002
  • Appl. No.:
    10/171447
  • Inventors:
    Kuriappan P. Alappat - Portland OR, US
    Brian Peebles - Cranford NJ, US
    Aniruddha Kundu - Portland OR, US
    Gerald Lebizay - Madison NJ, US
  • Assignee:
    Intel Corporation - Santa Clara CA
  • International Classification:
    H04L 12/50
    H04Q 11/00
  • US Classification:
    370360
  • Abstract:
    A backplane employed in a switch fabric, having the capability to allow signal communication between at least two modules. Two or more of the modules being adapted to employ different topologies from the following types of topologies: star, dual star, mesh, and cascaded mesh.
  • Power Management Control System And Method

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  • US Patent:
    8228038, Jul 24, 2012
  • Filed:
    Dec 23, 2009
  • Appl. No.:
    12/646139
  • Inventors:
    Kevin R. Mullen - Portland OR, US
    Kuriappan P. Alappat - Portland OR, US
    Don J. Nguyen - Portland OR, US
  • Assignee:
    Intel Corporation - Santa Clara CA
  • International Classification:
    H02J 7/00
    H02J 7/06
  • US Classification:
    320135, 320162, 320164
  • Abstract:
    A power management system includes a sensor to detect current output from a battery, a first comparator to compare the battery current to a first reference value, and a burst controller to perform a first power control operation based on said comparison. The power control operation reduces power consumed by the battery in order to cause the battery current to fall below the first reference value. This may be accomplished by reducing or shutting down power to one or more functions or features of a host system that includes or is coupled to receive power from the battery. The host system may include or correspond to a mobile phone and/or any of a number of other electronic devices.
  • Limiting Peak Audio Power In Mobile Devices

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  • US Patent:
    8577056, Nov 5, 2013
  • Filed:
    Jun 30, 2010
  • Appl. No.:
    12/827317
  • Inventors:
    Kuriappan P. Alappat - Portland OR, US
    Vijayakumaran V. Nair - Austin TX, US
  • Assignee:
    Intel Corporation - Santa Clara CA
  • International Classification:
    H04B 15/00
  • US Classification:
    381 941, 381 948
  • Abstract:
    Systems and methods of limiting peak audio power in mobile devices may include a high pass filter and a burst module to detect a burst load condition in a mobile device. The burst module can also apply the high pass filter to an audio signal of the mobile device in response to the burst load condition to obtain a filtered signal, and transmit the filtered audio signal to a speaker of the mobile device.
  • Computer System With Dedicated System Management Buses

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  • US Patent:
    20030115397, Jun 19, 2003
  • Filed:
    Dec 14, 2001
  • Appl. No.:
    10/014904
  • Inventors:
    Pete Hawkins - San Luis Obispo CA, US
    Kuriappan Alappat - Portland OR, US
  • International Classification:
    G06F013/14
  • US Classification:
    710/305000
  • Abstract:
    A system includes a central management agent and one or more field replaceable unit type specific management buses. Each field replaceable unit type specific management bus may couple the central management agent to a set of field replaceable units, with each unit in each set being the same type of field replaceable unit.

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