Kurt E Sincerbox

US Patent:

20120285730, Nov 15, 2012

Filed:

May 12, 2011

Appl. No.:

13/106383

Inventors:

Artur DARBINYAN - Santa Clara CA, US
David T. CHIN - Cupertino CA, US
Kurt E. SINCERBOX - San Jose CA, US

Assignee:

NATIONAL SEMICONDUCTOR CORPORATION - Santa Clara CA

International Classification:

H05K 1/09
B28B 11/14

US Classification:

174251, 264157

Abstract:

A method of fabricating chip carriers suitable for use in packaging integrated circuits and other electronic, electro-mechanical and opto-electronic devices is described. In general, a number of wires (or wires and rods) are arranged in parallel in a wiring fixture. After the wires are positioned, they are encapsulated to form an encapsulated wiring block. The wiring block is then sliced to form a number of discrete panels. Preferably, the various wires are geometrically positioned such that each resulting panel has a large number of device areas defined therein. The encapsulant in each panel effectively forms a substrate and the wire segments in each panel form conductive vias that extend through the substrate. The resulting panels/chip carriers can then be used in a wide variety of packaging applications.

US Patent:

20120057313, Mar 8, 2012

Filed:

Sep 3, 2010

Appl. No.:

12/876002

Inventors:

Artur DARBINYAN - Santa Clara CA, US
Kurt E. SINCERBOX - San Jose CA, US
David T. CHIN - Cupertino CA, US

Assignee:

NATIONAL SEMICONDUCTOR CORPORATION - Santa Clara CA

International Classification:

H05K 5/00
B29C 39/10
H05K 7/00

US Classification:

361752, 361748, 264257

Abstract:

Methods and arrangements for packaging system level electronics are described. In one aspect, an external skin of the package is formed from isolation paper. In some embodiments, the isolation paper is formed into a box. A printed circuit board is placed within the isolation paper skin and is substantially completely surrounded by a potting material that substantially completely fills the skin. The potting material is cured to solidify the potting material within the isolation paper box and to adhere the potting material to the isolation paper such that the isolation paper forms a skin for a brick of potting material that encapsulates the printed circuit board. The isolation paper skin includes at least one opening that permits an interconnect to be exposed through the skin. With this arrangement, a packaged electronics device is provided and the isolation paper forms the exposed outer surface of the packaged electronics device. The described package is particularly well suited for use in packaging system level power electronics such as power supplies.

US Patent:

20230005880, Jan 5, 2023

Filed:

Jun 30, 2021

Appl. No.:

17/364735

Inventors:

- Dallas TX, US
Ashok Surendra Prabhu - San Jose CA, US
Hau Nguyen - San Jose CA, US
Kurt Edward Sincerbox - San Jose CA, US
Makoto Shibuya - Tokyo, JP

International Classification:

H01L 23/00
H01L 25/065
H01L 21/56
H01L 23/498
H01L 23/367
H01L 23/31
H01L 21/48

Abstract:

In a described example, an apparatus includes: a first package substrate having a die mount surface; a semiconductor die flip chip mounted to the first package substrate on the die mount surface, the semiconductor die having post connects having proximate ends on bond pads on an active surface of the semiconductor die, and extending to distal ends away from the semiconductor die having solder bumps, wherein the solder bumps form solder joints to the package substrate; a second package substrate having a thermal pad positioned with the thermal pad over a backside surface of the semiconductor die, the thermal pad comprising a thermally conductive material; and a mold compound covering a portion of the first package substrate, a portion of the second package substrate, the semiconductor die, and the post connects, thermal pad having a surface exposed from the mold compound.

US Patent:

20200235067, Jul 23, 2020

Filed:

Jan 22, 2019

Appl. No.:

16/253680

Inventors:

- Dallas TX, US
Kurt Sincerbox - San Jose CA, US
Vivek Arora - San Jose CA, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 23/00
H01L 23/538
H01L 23/31
H01L 25/07
H01L 25/00

Abstract:

A packaged electronic device includes a multilayer substrate, including a first side, a first layer having a first plurality of conductive structures along the first side, and a second layer having a second plurality of conductive structures, a semiconductor die soldered to a first set of the conductive structures, a conductive clip directly connected to one of the conductive structures of the first layer and to a second side of the semiconductor die, and a package structure that encloses the semiconductor die and a portion of the conductive clip.