Kyung Yoon Choi

US Patent:

6428377, Aug 6, 2002

Filed:

Jun 14, 2000

Appl. No.:

09/593194

Inventors:

Kyung Cheol Choi - Mahwah NJ

Assignee:

Hynix Semiconductor Inc. - Seoul

International Classification:

H01J 902

US Classification:

445 24

Abstract:

A colored DC plasma display panel having a plurality of sub-pixels organized in a matrix configuration. The color DC plasma display panel includes a first plate having a first substrate. A plurality of rows of cathodes are formed on the first substrate which include a plurality of holes therein spaced along each cathode row; preferably one hole for each sub-pixel. A dielectric layer covers the cathode rows and the substrate, and a plurality of holes are formed in the dielectric layer which align with the holes in the cathodes. The color DC plasma display panel further includes a second plate having a second substrate and a pluarility of rows of anodes formed on and extending along the length of the second substrate. The anodes reside in channels created between a pluarality of rows of barrier ribs formed on the second substrate. The plasma display panel is formed by combining the first plate and the second plate so that the anodes rows on the second plate run substantially orthogonal to the cathode rows on the first plate.

US Patent:

6504292, Jan 7, 2003

Filed:

Jul 30, 1999

Appl. No.:

09/365059

Inventors:

Kyung Moon Choi - Scotch Plains NJ
Sungho Jin - Millington NJ
Gregory Peter Kochanski - Dunellen NJ
Wei Zhu - Warren NJ

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

H01J 113

US Classification:

313310, 313309, 313311, 313326, 313336, 313351, 313346 R

Abstract:

In accordance with the invention, an improved conductive nanostructure assembly comprises an array of metallized nanostructures disposed on a conductive substrate. The substrate can also be metallized. Such assemblies provide continuous electron transport from the substrate to the tips of the nanostructures. Several ways of making such assemblies are described along with several devices employing the assemblies.

US Patent:

6538367, Mar 25, 2003

Filed:

Aug 6, 1999

Appl. No.:

09/369802

Inventors:

Kyung Moon Choi - Scotch Plains NJ
Sungho Jin - Millington NJ
Gregory Peter Kochanski - Dunellen NJ
Wei Zhu - Warren NJ

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

H01J 102

US Classification:

313309, 313495, 313308

Abstract:

This invention is predicated on applicants discovery that a highly oriented nanoconductor structure alone does not guarantee efficient field emission. To the contrary, the conventional densely populated, highly oriented structures actually yield relatively poor field emission characteristics. Applicants have determined that the individual nanoconductors in conventional assemblies are so closely spaced that they shield each other from effective field concentration at the ends, thus diminishing the driving force for efficient electron emission. In accordance with the invention, an improved field emitting nanoconductors assembly (a âlow density nanoconductor assemblyâ) comprises an array of nanoconductors which are highly aligned but spaced from each other no closer than 10% of the height of the nanoconductors. In this way, the field strength at the ends will be at least 50% of the maximal field concentration possible. Several ways of making the optimally low density assemblies are described along with several devices employing the assemblies.

US Patent:

63227134, Nov 27, 2001

Filed:

Jul 15, 1999

Appl. No.:

9/354928

Inventors:

Kyung Moon Choi - Scotch Plains NJ
Sungho Jin - Millington NJ

Assignee:

Agere Systems Guardian Corp. - Orlando FL

International Classification:

B82B 100

US Classification:

216 38

Abstract:

In accordance with the invention, nanoscale connectors particularly useful for connecting microscale devices comprise free-standing nanoscale conductors. The nanoscale conductors are conveniently fabricated in sets of controlled, preferably equal length by providing a removable substrate, growing conductive nanotubes or nanowires on the substrate, equalizing the length of the nanoscale conductors, and removing the substrate. Preferably the removable substrate is soluble, leaving a collection of free standing nanoscale connectors in suspension or solution.

US Patent:

61603481, Dec 12, 2000

Filed:

May 18, 1998

Appl. No.:

9/080561

Inventors:

Kyung Cheol Choi - Mahwah NJ

Assignee:

Hyundai Electronics America, Inc. - San Jose CA

International Classification:

H01J 1749

US Classification:

313584

Abstract:

A colored DC plasma display panel having a plurality of sub-pixels organized in a matrix configuration. The color DC plasma display panel includes a first plate having a first substrate. A plurality of rows of cathodes are formed on the first substrate which include a plurality of holes therein spaced along each cathode row; preferably one hole for each sub-pixel. A dielectric layer covers the cathode rows and the substrate, and a plurality of holes are formed in the dielectric layer which align with the holes in the cathodes. The color DC plasma display panel further includes a second plate having a second substrate and a pluarility of rows of anodes formed on and extending along the length of the second substrate. The anodes reside in channels created between a pluarlity of rows of barrier ribs formed on the second substrate. The plasma display panel is formed by combining the first plate and the second plate so that the anodes rows on the second plate run substantially orthogonal to the cathode rows on the first plate.