Lan Kim Phan

US Patent:

8316176, Nov 20, 2012

Filed:

Feb 17, 2010

Appl. No.:

12/707552

Inventors:

Lan D. Phan - Laguna Hills CA, US
Dominic S. Suryabudi - Irvine CA, US

Assignee:

Western Digital Technologies, Inc. - Irvine CA

International Classification:

G06F 12/00

US Classification:

711103, 36518533

Abstract:

A non-volatile semiconductor memory is disclosed comprising a memory device including a memory array having a plurality of blocks, each block comprising a plurality of memory segments. A plurality of logical block address (LBA) ranges are defined each identifying a plurality of LBA addresses, wherein at least one block is assigned to each LBA range. A plurality of write commands are received from a host, wherein each write command identifies at least one LBA. Data is written for each write command to the memory device. During a garbage collection operation, a memory segment storing valid write data is identified to be relocated, and the valid write data is relocated to a memory segment in a block of the corresponding LBA range.

US Patent:

8612669, Dec 17, 2013

Filed:

Jun 28, 2010

Appl. No.:

12/824434

Inventors:

Matthew Call - Ladera Ranch CA, US
Lan D. Phan - Laguna Hills CA, US

Assignee:

Western Digital Technologies, Inc. - Irvine CA

International Classification:

G06F 12/16
G11C 16/34
G11C 11/406

US Classification:

711103, 711106, 36518525, 365222

Abstract:

Systems and methods for retaining data in non-volatile solid-state are disclosed in which refresh copy operations are performed on data stored in non-volatile solid-state memory. A controller can comprise a data retention module configured to issue copy commands within different periods of time, and to maintain usage data on a storage subsystem. A refresh copy operation helps ensure that data written to memory retain integrity by causing data to be programmed again onto the memory, which minimizes the risk of data error caused by electron leak in the non-volatile solid-state memory. One or more data structures may be used to determine memory blocks that require refresh copy operations. In one embodiment, a validity bit array is used to track blocks that contain valid data. In another embodiment, a least recently used list is used to track blocks that have been least recently written.

US Patent:

20210141543, May 13, 2021

Filed:

Jan 20, 2021

Appl. No.:

17/153719

Inventors:

- San Jose CA, US
Dominic S. SURYABUDI - Irvine CA, US
Lan D. PHAN - Laguna Hills CA, US

International Classification:

G06F 3/06
G06F 12/02
G06F 11/14

Abstract:

A data storage subsystem is disclosed that implements a process for storing and/or reconstructing system data, such as a system mapping table. In certain embodiments, table pages are systematically copied, or flushed, to non-volatile memory in a progressive manner, according to a fixed ratio of flushed table pages per table update trigger, thereby facilitating write and/or load efficiency. Full or partial reconstruction of a table may be performed within a bounded number of operations based on the size of the table, the ratio implemented, and/or other characteristics.

US Patent:

20190347017, Nov 14, 2019

Filed:

Jul 26, 2019

Appl. No.:

16/523951

Inventors:

- San Jose CA, US
Dominic S. SURYABUDI - Irvine CA, US
Lan D. PHAN - Laguna Hills CA, US

International Classification:

G06F 3/06
G06F 11/14
G06F 12/02

Abstract:

A data storage subsystem is disclosed that implements a process for storing and/or reconstructing system data, such as a system mapping table. In certain embodiments, table pages are systematically copied, or flushed, to non-volatile memory in a progressive manner, according to a fixed ratio of flushed table pages per table update trigger, thereby facilitating write and/or load efficiency. Full or partial reconstruction of a table may be performed within a bounded number of operations based on the size of the table, the ratio implemented, and/or other characteristics.

US Patent:

20170031607, Feb 2, 2017

Filed:

Oct 14, 2016

Appl. No.:

15/294063

Inventors:

- Irvine CA, US
Lan D. PHAN - Trabuco Canyon CA, US

International Classification:

G06F 3/06
G06F 12/02

Abstract:

Embodiments of this disclosure relate to improving solid-state non-volatile memory management. Embodiments improve the management of solid-state non-volatile memory by providing an execution manager responsible for controlling the timing of providing a request to a memory unit for execution. In embodiments, the execution manager traverses a list of received requests for memory access and dispatches commands for execution. In embodiments, if a request is directed to memory units which have reached a threshold for outstanding requests, the request may be skipped so that other requests can be dispatched for memory units which have not yet reached the threshold.

US Patent:

20160216910, Jul 28, 2016

Filed:

Apr 4, 2016

Appl. No.:

15/089601

Inventors:

- Rancho Santa Margarita CA, US
Lan Dinh Phan - Trabuco Canyon CA, US

International Classification:

G06F 3/06
G11C 11/56

Abstract:

Reduced spatial redundancy of lower bits data can provide data protection for a flash memory having MLC NAND devices operated in page mode. An interrupted write operation of most significant bit pages can corrupt previously written data in lower bit pages. The lower bits redundant memory can assist in restoring the data, using less than a full back up storage.

US Patent:

20160048352, Feb 18, 2016

Filed:

Oct 26, 2015

Appl. No.:

14/923000

Inventors:

- Irvine CA, US
Dominic S. SURYABUDI - IRVINE CA, US
Lan D. PHAN - Laguna Hills CA, US

International Classification:

G06F 3/06

Abstract:

A data storage subsystem is disclosed that implements a process for storing and/or reconstructing system data, such as a system mapping table. In certain embodiments, table pages are systematically copied, or flushed, to non-volatile memory in a progressive manner, according to a fixed ratio of flushed table pages per table update trigger, thereby facilitating write and/or load efficiency. Full or partial reconstruction of a table may be performed within a bounded number of operations based on the size of the table, the ratio implemented, and/or other characteristics.

US Patent:

20160041773, Feb 11, 2016

Filed:

Oct 16, 2015

Appl. No.:

14/885018

Inventors:

- Irvine CA, US
Lan D. PHAN - Laguna Hills CA, US

International Classification:

G06F 3/06

Abstract:

Embodiments of this disclosure relate to improving solid-state non-volatile memory management. Embodiments improve the management of solid-state non-volatile memory by providing an execution manager responsible for controlling the timing of providing a request to a memory unit for execution. In embodiments, the execution manager traverses a list of received requests for memory access and dispatches commands for execution. In embodiments, if a request is directed to memory units which have reached a threshold for outstanding requests, the request may be skipped so that other requests can be dispatched for memory units which have not yet reached the threshold.