Laura A Potter

US Patent:

20030042935, Mar 6, 2003

Filed:

Jul 1, 2002

Appl. No.:

10/186770

Inventors:

Terence Potter - Austin TX, US
James Blomgren - Austin TX, US
Laura Potter - Austin TX, US
Fritz Boehm - Dripping Springs TX, US

International Classification:

H03K019/096

US Classification:

326/098000

Abstract:

A static output signal is generated using a static storage element () and transmitted to a NDL gate () over a transmission path () that is characterized by a user-specified multi-cycle timing constraint that is used to create appropriate verification tests of the apparatus. The multi-cycle timing constraint may be a pragma that is interpreted by the compiler of a timing analysis tool such as PATHMILL to automatically check the set-up and hold times of the static signal relative to the rising edge or falling edge of user-specified clock signal pulses. The same pragma is interpreted by the compiler of a functional verification tools such as VIS to create statements that test the behavior of the apparatus during the clock signal pulses other than the user-specified clock signal pulses tested by the timing analysis tool.