Lawrence W Wong

US Patent:

6566757, May 20, 2003

Filed:

Mar 1, 2000

Appl. No.:

09/516650

Inventors:

Indrajit Banerjee - San Jose CA
Lawrence D. Wong - Beaverton OR
Marnie L. Harker - Campbell CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 2348

US Classification:

257758, 257759, 257760

Abstract:

An interconnect structure for microelectronic devices includes interconnect lines having dielectric material disposed therebetween as an intralayer dielectric, and a capping structure, also disposed between the interconnect lines, that reduces outgassing from the material. Typical embodiments include fluorinated dielectric materials, such as amorphous fluorinated carbon. The capping structure also acts as a moisture barrier to prevent moisture from penetrating into the fluorinated material and combining therewith to produce corrosive chemicals. The capping structure is formed in-situ so that the fluorinated dielectric material is not exposed to moisture prior to the formation of the capping structure.

US Patent:

6593650, Jul 15, 2003

Filed:

Jan 15, 2002

Appl. No.:

10/050463

Inventors:

Steven Towle - Sunnyvale CA
Ebrahim Andideh - Portland OR
Lawrence D. Wong - Beaverton OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 2312

US Classification:

257701, 257758, 257760

Abstract:

A low dielectric constant material having a first fluorine concentration in a near-surface portion and a second fluorine concentration in an interior portion provides an insulator suitable for use in integrated circuits. In a further aspect of the present invention, fluorine is depleted from a near-surface portion of a fluorine containing dielectric material by a reducing plasma. Fluorine in fluorinated low-k dielectric materials, such as SiOF, amorphous fluorinated carbon (a-F:C) and parylene-AF4, can react with surrounding materials such as metals and Si N , causing blisters and delamination. Treatment of these fluorinated low-k dielectric materials in a reducing plasma, which may be produced from precursor gases such as H or NH , depletes the surface region of fluorine and hence reduces reaction with surrounding materials and F outgassing. By selecting an appropriate point in the integration flow, specific interfaces which are most susceptible to F-attack can be targeted for depletion.

US Patent:

6846737, Jan 25, 2005

Filed:

Aug 15, 2000

Appl. No.:

09/639625

Inventors:

Steven Towle - Sunnyvale CA, US
Ebrahim Andideh - Portland OR, US
Lawrence D. Wong - Beaverton OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 214763

US Classification:

438622, 438626, 438634

Abstract:

A low dielectric constant material having a first fluorine concentration in a near-surface portion and a second fluorine concentration in an interior portion provides an insulator suitable for use in integrated circuits. In a further aspect of the present invention, fluorine is depleted from a near-surface portion of a fluorine containing dielectric material by a reducing plasma. Fluorine in fluorinated low-k dielectric materials, such as SiOF, amorphous fluorinated carbon (a-F:C) and parylene-AF4, can react with surrounding materials such as metals and SiN, causing blisters and delamination. Treatment of these fluorinated low-k dielectric materials in a reducing plasma, which may be produced from precursor gases such as Hor NH, depletes the surface region of fluorine and hence reduces reaction with surrounding materials and F outgassing. By selecting an appropriate point in the integration flow, specific interfaces which are most susceptible to F-attack can be targeted for depletion.

US Patent:

7879731, Feb 1, 2011

Filed:

Apr 11, 2007

Appl. No.:

11/733764

Inventors:

Kenneth S. Collins - San Jose CA, US
Hiroji Hanawa - Sunnyvale CA, US
Kartik Ramaswamy - San Jose CA, US
Shahid Rauf - Pleasanton CA, US
Kallol Bera - San Jose CA, US
Lawrence Wong - Fremont CA, US
Walter R. Merry - Sunnyvale CA, US
Matthew L. Miller - Fremont CA, US
Steven C. Shannon - San Mateo CA, US
Andrew Nguyen - San Jose CA, US
James P. Cruse - Soquel CA, US
James Carducci - Sunnyvale CA, US
Troy S. Detrick - Los Altos CA, US
Subhash Deshmukh - San Jose CA, US
Jennifer Y. Sun - Sunnyvale CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 21/302

US Classification:

438714, 438 8, 438706, 15634548

Abstract:

A method is provided for processing a workpiece in a plasma reactor chamber having electrodes including at least a ceiling electrode and a workpiece support electrode. The method includes coupling respective RF power sources of respective VHF frequencies f and f to either (a) respective ones of the electrodes or (b) a common one of the electrodes, where f is sufficiently high to produce a center-high non-uniform plasma ion distribution and f is sufficiently low to produce a center-low non-uniform plasma ion distribution. The method further includes adjusting a ratio of an RF parameter at the f frequency to the RF parameter at the f frequency so as to control plasma ion density distribution, the RF parameter being any one of RF power, RF voltage or RF current.

US Patent:

7884025, Feb 8, 2011

Filed:

Apr 11, 2007

Appl. No.:

11/733767

Inventors:

Kenneth S. Collins - San Jose CA, US
Hiroji Hanawa - Sunnyvale CA, US
Kartik Ramaswamy - San Jose CA, US
Shahid Rauf - Pleasanton CA, US
Kallol Bera - San Jose CA, US
Lawrence Wong - Fremont CA, US
Walter R. Merry - Sunnyvale CA, US
Matthew L. Miller - Fremont CA, US
Steven C. Shannon - San Mateo CA, US
Andrew Nguyen - San Jose CA, US
James P. Cruse - Soquel CA, US
James Carducci - Sunnyvale CA, US
Troy S. Detrick - Los Altos CA, US
Subhash Deshmukh - San Jose CA, US
Jennifer Y. Sun - Sunnyvale CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 21/302

US Classification:

438714, 438 8, 438706, 438710, 15634548

Abstract:

In a plasma reactor chamber a ceiling electrode and a workpiece support electrode, respective RF power sources of respective VHF frequencies f and f are coupled to either respective ones of the electrodes or to a common one of the electrodes, where f is sufficiently high to produce a center-high non-uniform plasma ion distribution and f is sufficiently low to produce a center-low non-uniform plasma ion distribution. Respective center ground return paths are provided for RF current passing directly between the ceiling electrode and the workpiece support electrode for the frequencies f and f, and an edge ground return path is provided for each of the frequencies f and f. The impedance of at least one of the ground return paths is adjusted so as to control the uniformity of the plasma ion density distribution.

US Patent:

7968469, Jun 28, 2011

Filed:

Apr 11, 2007

Appl. No.:

11/733984

Inventors:

Kenneth S. Collins - San Jose CA, US
Hiroji Hanawa - Sunnyvale CA, US
Kartik Ramaswamy - San Jose CA, US
Shahid Rauf - Pleasanton CA, US
Kallol Bera - San Jose CA, US
Lawrence Wong - Fremont CA, US
Walter R. Merry - Sunnyvale CA, US
Matthew L. Miller - Fremont CA, US
Steven C. Shannon - San Mateo CA, US
Andrew Nguyen - San Jose CA, US
James P. Cruse - Soquel CA, US
James Carducci - Sunnyvale CA, US
Troy S. Detrick - Los Altos CA, US
Subhash Deshmukh - San Jose CA, US
Jennifer Y. Sun - Sunnyvale CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 21/302

US Classification:

438714, 438 9, 438706, 15634547

Abstract:

A method for processing a workpiece in a plasma reactor chamber includes coupling RF power at a first VHF frequency f to a plasma via one of the electrodes of the chamber, and providing a center ground return path for RF current passing directly between the ceiling electrode and the workpiece support electrode for the frequency f. The method further includes providing a variable height edge ground annular element and providing a ground return path through the edge ground annular element for the frequency f. The method controls the uniformity of plasma ion density distribution by controlling the distance between the variable height edge ground annular element and one of: (a) height of ceiling electrode or (b) height of workpiece support electrode.

US Patent:

7972469, Jul 5, 2011

Filed:

Apr 22, 2007

Appl. No.:

11/738505

Inventors:

Hiroji Hanawa - Sunnyvale CA, US
Andrew Nguyen - San Jose CA, US
Keiji Horioka - Tokyo, JP
Kallol Bera - San Jose CA, US
Kenneth S. Collins - San Jose CA, US
Lawrence Wong - Fremont CA, US
Martin Jeff Salinas - San Jose CA, US
Roger A. Lindley - Santa Clara CA, US
Hong S. Yang - Pleasanton CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 21/00

US Classification:

15634546

Abstract:

Embodiments of the present invention relate to plasma processing apparatus and methods of use thereof. In some embodiments, a plasma control magnet assembly includes a plurality of magnets arranged in a predetermined pattern that generate a magnetic field having a strength greater than 10 Gauss in a region proximate the assembly and less than 10 Gauss in a region remote from the assembly.

US Patent:

7988815, Aug 2, 2011

Filed:

Jul 26, 2007

Appl. No.:

11/828568

Inventors:

Shahid Rauf - Pleasanton CA, US
Kenneth S. Collins - San Jose CA, US
Kallol Bera - San Jose CA, US
Kartik Ramaswamy - San Jose CA, US
Hiroji Hanawa - Sunnyvale CA, US
Andrew Nguyen - San Jose CA, US
Steven C. Shannon - San Mateo CA, US
Lawrence Wong - Fremont CA, US
Satoru Kobayashi - Mountain View CA, US
Troy S. Detrick - Los Altos CA, US
James P. Cruse - Santa Cruz CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

C23C 16/00
H01L 21/306

US Classification:

15634543, 15634547, 15634548, 118723 R, 118723 E, 118723 I

Abstract:

RF ground return current flow is diverted away from asymmetrical features of the reactor chamber by providing bypass current flow paths. One bypass current flow path avoids the pumping port in the chamber floor, and comprises a conductive symmetrical grill extending from the side wall to the grounded pedestal base. Another bypass current flow path avoids the wafer slit valve, and comprises an array of conductive straps bridging the section of the sidewall occupied by the slit valve.