Leland M Swanson

Address:

4075 40 Ave S, Fargo, ND 58104

Phone:

(701)3562888

VIN:

JTMBD32V776030045

Make:

TOYOTA

Model:

RAV4

Year:

2007

US Patent:

6362065, Mar 26, 2002

Filed:

Feb 26, 2001

Appl. No.:

09/794709

Inventors:

Leland S. Swanson - McKinney TX
Gregory E. Howard - Dallas TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21330

US Classification:

438344, 257198, 438343, 438345

Abstract:

The present invention relates to a method of forming a bipolar transistor or a heterojunction bipolar transistor. The method comprises forming a collector region associated with a semiconductor substrate, and forming a base region base region over at least a portion of the collector region. The method further comprises forming a diffusion blocking layer over the base region, and forming an emitter polysilicon region over the diffusion blocking layer. The diffusion blocking layer reduces an amount of diffusion from the emitter polysilicon region into the base region, thereby allowing improved process control and emitter/base doping profile, leading to improved transistor performance. In addition, the present invention relates to a heterojunction bipolar transistor, and comprises a collector region, and a graded profile SiGe base layer overlying the collector region. The transistor further comprises a diffusion blocking layer overlying the graded profile SiGe base layer, and an emitter layer overlying the diffusion blocking layer. The diffusion blocking layer is operable to retard a diffusion of dopants therethrough from the emitter layer to the graded profile SiGe base layer, thereby allowing for a reduction in the thickness of the layer comprising a graded profile SiGe layer and a buffer layer.

US Patent:

6376285, Apr 23, 2002

Filed:

May 20, 1999

Appl. No.:

09/314983

Inventors:

Keith A. Joyner - Richardson TX
Leland S. Swanson - McKinney TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2100

US Classification:

438149, 438150, 438453, 205656, 205660, 205662, 205674

Abstract:

An epitaxial layer of silicon is grown on a layer of partially-oxidized porous silicon, then covered by a capping layer which provides structural support and prevents oxidation of the epitaxial layer. A high-temperature anneal allows the partially oxidized silicon layer to separate into distinct layers of silicon and SiO2, producing a buried oxide layer. This method provides a low cost means of producing silicon-on-insulator (SOI) wafers.

US Patent:

6376859, Apr 23, 2002

Filed:

Jul 1, 1999

Appl. No.:

09/346763

Inventors:

Leland S. Swanson - McKinney TX
Keith A. Joyner - Richardson TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2904

US Classification:

257 49, 257 82, 257 84, 257638

Abstract:

Varying the porosity through the thickness of a porous silicon layer allows conflicting needs to be met by the same layer: a low porosity surface layer allows a high-quality epitaxial layer of silicon to be grown, or can provide structural support, while greater porosity in other portions of the layer increases circuit isolation and provides stress relief between layers.

US Patent:

6417523, Jul 9, 2002

Filed:

Jan 13, 2000

Appl. No.:

09/482760

Inventors:

Leland S. Swanson - McKinney TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01J 162

US Classification:

257 88, 257 81, 3131691, 3131693, 313505, 313506, 313512

Abstract:

An edge emitter ( ) includes a diode array ( ) with an emissive edge ( ). The diode array ( ) is formed on a substrate layer ( ) that includes integrated driver circuits ( ) to power the diode array ( ). Dielectric posts ( ) are formed on the substrate layer to provide optical isolation for each light emitting diode ( ) of the diode array ( ). A reflective metal coating ( ) is formed on the substrate layer ( ) and the dielectric posts ( ). A light guide layer ( ) is formed on the reflective coating ( ) followed by the formation of an anode layer ( ), an organic semiconductor layer ( ), and a cathode layer ( ). Vias ( ) are formed from the anode layer ( ) and the cathode layer ( ) to the integrated driver circuits ( ). The emissive edge ( ) of each light emitting diode ( ) in the diode array ( ) has a height and width approximately one-tenth that of its length.

US Patent:

6420933, Jul 16, 2002

Filed:

Nov 20, 2000

Appl. No.:

09/716597

Inventors:

Neil Gibson - Richardson TX
Leland S. Swanson - McKinney TX
Marco Corsi - Parker TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03F 318

US Classification:

330263, 330267, 330288

Abstract:

A current-to-current impedance converter re-circulates the driver transistor collector current back into the output current path to generate an error current that has two portions including a DC offset portion and a second order in 1/ portion. Since the error current has no first order in 1/ portion, the current-to-current ronverter exhbits very low distortion.

US Patent:

6455393, Sep 24, 2002

Filed:

Oct 2, 2000

Appl. No.:

09/677456

Inventors:

Leland S. Swanson - McKinney TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2176

US Classification:

438422, 438221, 438459, 438692

Abstract:

A method of fabricating an integrated circuit having active components, conductors and isolation regions on a substrate is disclosed, including patterning and etching a portion of at least one of said isolation regions to expose a first area of said substrate, depositing a mask layer over said integrated circuit including said first area, patterning an a itching said mask layer to expose a second area of said substrate within said first area, converting a portion of said substrate to a selectively etchable material, wherein said selectively etchable material lies in an area subjacent to said second area and extends only partially to the bottom surface of said substrate, selectively etching said selectively etchable material to form a void, removing said mask layer to expose said isolation region, depositing a dielectric layer over said void wherein said dielectric layer extends at least to the height of said isolation region and covers the top surface of said wafer, polishing the surface of said dielectric layer until the surface is planar and the top surface of said isolation region is exposed, and forming at least one patterned conductive layer over the surface of said dielectric layer that is coplanar with the surface of said isolation region.

US Patent:

6503838, Jan 7, 2003

Filed:

Oct 2, 2000

Appl. No.:

09/677728

Inventors:

Leland S. Swanson - McKinney TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2100

US Classification:

438692, 438719, 438723, 438735, 438745

Abstract:

A method of fabricating an integrated circuit having active components, conductors and isolation regions on a substrate is disclosed, including forming a portion of an isolation region to expose a first area of the substrate, depositing a mask layer over the integrated circuit including the first area, forming the mask layer to expose a second area of the substrate within the first area, converting a portion of the substrate to a selectively etchable material in an area subjacent to the second area and extending only partially to the bottom surface of the substrate, selectively etching this etchable material to form a void, removing the mask layer to expose the isolation region, depositing a conductive layer over all exposed surfaces of the substrate comprising the void and the isolation region, depositing a dielectric layer over the conductive layer extending at least to the height of the isolation region, polishing the surface of the dielectric layer until the surface is planar and the top surface of the isolation region is exposed, and forming at least one patterned conductive layer over the surface of the dielectric layer that is coplanar with the surface of the isolation region.

US Patent:

6528426, Mar 4, 2003

Filed:

Oct 15, 1999

Appl. No.:

09/419176

Inventors:

Leif C. Olsen - Plano TX
Leland S. Swanson - McKinney TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21302

US Classification:

438689, 694700

Abstract:

An inlaid interconnect fabrication method using a silicon carbide polish stop layer for protection of mechanically weak dielectric such as porous silicon dioxide (xerogel) during chemical mechanical polishing.