Leland Swanson

US Patent:

6362065, Mar 26, 2002

Filed:

Feb 26, 2001

Appl. No.:

09/794709

Inventors:

Leland S. Swanson - McKinney TX
Gregory E. Howard - Dallas TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21330

US Classification:

438344, 257198, 438343, 438345

Abstract:

The present invention relates to a method of forming a bipolar transistor or a heterojunction bipolar transistor. The method comprises forming a collector region associated with a semiconductor substrate, and forming a base region base region over at least a portion of the collector region. The method further comprises forming a diffusion blocking layer over the base region, and forming an emitter polysilicon region over the diffusion blocking layer. The diffusion blocking layer reduces an amount of diffusion from the emitter polysilicon region into the base region, thereby allowing improved process control and emitter/base doping profile, leading to improved transistor performance. In addition, the present invention relates to a heterojunction bipolar transistor, and comprises a collector region, and a graded profile SiGe base layer overlying the collector region. The transistor further comprises a diffusion blocking layer overlying the graded profile SiGe base layer, and an emitter layer overlying the diffusion blocking layer. The diffusion blocking layer is operable to retard a diffusion of dopants therethrough from the emitter layer to the graded profile SiGe base layer, thereby allowing for a reduction in the thickness of the layer comprising a graded profile SiGe layer and a buffer layer.

US Patent:

6376859, Apr 23, 2002

Filed:

Jul 1, 1999

Appl. No.:

09/346763

Inventors:

Leland S. Swanson - McKinney TX
Keith A. Joyner - Richardson TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2904

US Classification:

257 49, 257 82, 257 84, 257638

Abstract:

Varying the porosity through the thickness of a porous silicon layer allows conflicting needs to be met by the same layer: a low porosity surface layer allows a high-quality epitaxial layer of silicon to be grown, or can provide structural support, while greater porosity in other portions of the layer increases circuit isolation and provides stress relief between layers.

US Patent:

6417523, Jul 9, 2002

Filed:

Jan 13, 2000

Appl. No.:

09/482760

Inventors:

Leland S. Swanson - McKinney TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01J 162

US Classification:

257 88, 257 81, 3131691, 3131693, 313505, 313506, 313512

Abstract:

An edge emitter ( ) includes a diode array ( ) with an emissive edge ( ). The diode array ( ) is formed on a substrate layer ( ) that includes integrated driver circuits ( ) to power the diode array ( ). Dielectric posts ( ) are formed on the substrate layer to provide optical isolation for each light emitting diode ( ) of the diode array ( ). A reflective metal coating ( ) is formed on the substrate layer ( ) and the dielectric posts ( ). A light guide layer ( ) is formed on the reflective coating ( ) followed by the formation of an anode layer ( ), an organic semiconductor layer ( ), and a cathode layer ( ). Vias ( ) are formed from the anode layer ( ) and the cathode layer ( ) to the integrated driver circuits ( ). The emissive edge ( ) of each light emitting diode ( ) in the diode array ( ) has a height and width approximately one-tenth that of its length.

US Patent:

6455393, Sep 24, 2002

Filed:

Oct 2, 2000

Appl. No.:

09/677456

Inventors:

Leland S. Swanson - McKinney TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2176

US Classification:

438422, 438221, 438459, 438692

Abstract:

A method of fabricating an integrated circuit having active components, conductors and isolation regions on a substrate is disclosed, including patterning and etching a portion of at least one of said isolation regions to expose a first area of said substrate, depositing a mask layer over said integrated circuit including said first area, patterning an a itching said mask layer to expose a second area of said substrate within said first area, converting a portion of said substrate to a selectively etchable material, wherein said selectively etchable material lies in an area subjacent to said second area and extends only partially to the bottom surface of said substrate, selectively etching said selectively etchable material to form a void, removing said mask layer to expose said isolation region, depositing a dielectric layer over said void wherein said dielectric layer extends at least to the height of said isolation region and covers the top surface of said wafer, polishing the surface of said dielectric layer until the surface is planar and the top surface of said isolation region is exposed, and forming at least one patterned conductive layer over the surface of said dielectric layer that is coplanar with the surface of said isolation region.

US Patent:

6503838, Jan 7, 2003

Filed:

Oct 2, 2000

Appl. No.:

09/677728

Inventors:

Leland S. Swanson - McKinney TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2100

US Classification:

438692, 438719, 438723, 438735, 438745

Abstract:

A method of fabricating an integrated circuit having active components, conductors and isolation regions on a substrate is disclosed, including forming a portion of an isolation region to expose a first area of the substrate, depositing a mask layer over the integrated circuit including the first area, forming the mask layer to expose a second area of the substrate within the first area, converting a portion of the substrate to a selectively etchable material in an area subjacent to the second area and extending only partially to the bottom surface of the substrate, selectively etching this etchable material to form a void, removing the mask layer to expose the isolation region, depositing a conductive layer over all exposed surfaces of the substrate comprising the void and the isolation region, depositing a dielectric layer over the conductive layer extending at least to the height of the isolation region, polishing the surface of the dielectric layer until the surface is planar and the top surface of the isolation region is exposed, and forming at least one patterned conductive layer over the surface of the dielectric layer that is coplanar with the surface of the isolation region.

US Patent:

6537607, Mar 25, 2003

Filed:

Nov 16, 2000

Appl. No.:

09/714672

Inventors:

Leland S. Swanson - McKinney TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

B05D 512

US Classification:

427 66, 427 68, 427 70

Abstract:

A method for forming an emissive layer for an electroluminescent display is provided that includes positioning a substrate ( ) in spaced relation to a port ( ) of a microeffusion cell ( ). The method then provides for transporting the substrate ( ) across the port ( ) at a substantially constant rate. The method then provides for effusing an emissive material from the port ( ) and adhering at least a portion of the emissive material effused from the port ( ) to a defined region of the substrate ( ) to form an emissive strip ( ) having a substantially constant width on the substrate ( ).

US Patent:

6552375, Apr 22, 2003

Filed:

Mar 4, 2002

Appl. No.:

10/091242

Inventors:

Leland S. Swanson - McKinney TX 75070
Gregory E. Howard - Dallas TX 75229

International Classification:

H01L 31072

US Classification:

257198

Abstract:

The present invention relates to a heterojunction bipolar transistor, and comprises a collector region, and a graded profile SiGe base layer overlying the collector region. The transistor further comprises a diffusion blocking layer overlying the graded profile SiGe base layer, and an emitter layer overlying the diffusion blocking layer. The diffusion blocking layer is operable to retard a diffusion of dopants therethrough from the emitter layer to the graded profile SiGe base layer, thereby allowing for a reduction in the thickness of the layer comprising a graded profile SiGe layer and a buffer layer. The thickness reduction allows increased Ge concentration in the base layer and the emitter/base doping profile is improved, each leading to improved transistor performance.

US Patent:

6580170, Jun 17, 2003

Filed:

Jun 2, 2001

Appl. No.:

09/873058

Inventors:

Leland S. Swanson - McKinney TX
Elizabeth G. Jacobs - Richardson TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2348

US Classification:

257753, 257643, 257723, 257725, 438402, 438424, 438433, 438473

Abstract:

An integrated circuit device with a low stress, thin film, protective overcoat having enhanced adhesion both to polymeric materials used in packaging semiconductor devices, and within the passivating film layers, including the following sequence of materials deposited by PECVD processing: a thin film of silicon dioxide, a layer of silicon nitride, oxy-nitride or silicon carbide, and a very thin topmost layer of silicon oxide.