Lester Wilson

US Patent:

6335226, Jan 1, 2002

Filed:

Feb 9, 2000

Appl. No.:

09/500507

Inventors:

Richard W. Arnold - McKinney TX
Lester L. Wilson - Sherman TX
Mahmood A. Siddiqui - Desoto TX
James A. Forster - Barrington RI

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2130

US Classification:

438123, 438108, 438118, 438456, 438611, 257734, 257737, 257784

Abstract:

A package for a semiconductor die having a header with a cavity. The cavity includes a floor, sidewalls and a plurality of vertically spaced apart rows along the cavity sidewalls, each row including a plurality of spaced apart bond fingers. An electrically insulating membrane, preferably silicon, is disposed over the floor of the cavity, the membrane including a plurality of bumps, a plurality of peripherally located membrane bond pads and an interconnect from each of the bumps to a membrane bond pad. Bond wires are connected between the membrane bond pads and the bond fingers on the plurality of rows. A semiconductor die is provided having a plurality of bond pads, each bond pad contacting one of the bumps on the membrane. The header includes a plurality of alternating layers of electrically conducting material and electrically insulating material, the bond fingers on the header each being coupled to one of the layers of electrically conducting material. Each layer of electrically conducting material can include a plurality of spaced apart interconnect lines, each line coupled to one of the bond fingers.

US Patent:

6376352, Apr 23, 2002

Filed:

Nov 1, 1999

Appl. No.:

09/431730

Inventors:

Richard W. Arnold - McKinney TX
Weldon Beardain - Denison TX
Lester L. Wilson - Sherman TX
James A. Forster - Barrington RI

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2144

US Classification:

438612, 438613, 438614, 438650, 22818022

Abstract:

A method of forming a membrane for use in conjunction with a semiconductor carrier and the membrane which includes an electrically insulating substrate and an interconnect pattern formed on the substrate. A stud is coupled to the interconnect pattern over the substrate by forming a gold ball, preferably by gold ball bonding techniques, and coating a portion of the gold ball with a compliant material, preferably an epoxy resin. The coating is filled with a material having sufficient hardness to be capable of penetrating the oxide film on the contact pads of semiconductor devices. The flakes are preferably silver or silver-based.

US Patent:

6489673, Dec 3, 2002

Filed:

Jun 15, 2001

Appl. No.:

09/880870

Inventors:

Richard W. Arnold - McKinney TX
Lester L. Wilson - Sherman TX
Mahmood A. Siddiqui - Desoto TX
James A. Forster - Barrington RI

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2352

US Classification:

257692, 257680, 257690, 257693, 257697, 257701, 257737, 257738, 257773, 257784, 257786

Abstract:

A package for a semiconductor die having a header with a cavity. The cavity includes a floor, sidewalls and a plurality of vertically spaced apart rows along the cavity sidewalls, each row including a plurality of spaced apart bond fingers. An electrically insulating membrane, preferably silicon, is disposed over the floor of the cavity, the membrane including a plurality of bumps, a plurality of peripherally located membrane bond pads and an interconnect from each of the bumps to a membrane bond pad. Bond wires are connected between the membrane bond pads and the bond fingers on the plurality of rows. A semiconductor die is provided having a plurality of bond pads, each bond pad contacting one of the bumps on the membrane. The header includes a plurality of alternating layers of electrically conducting material and electrically insulating material, the bond fingers on the header each being coupled to one of the layers of electrically conducting material. Each layer of electrically conducting material can include a plurality of spaced apart interconnect lines, each line coupled to one of the bond fingers.

US Patent:

6553661, Apr 29, 2003

Filed:

Jan 4, 2001

Appl. No.:

09/754834

Inventors:

Richard W. Arnold - McKinney TX
Lester Wilson - Sherman TX
James Forster - Barrington RI

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H05K 302

US Classification:

29847, 29842, 29844, 29853, 324754

Abstract:

A test structure that is readily and inexpensively configurable to interface with dies having different bond pad configurations is achieved by providing a blank test membrane having a conductive coating or a matrix of conductive lines formed thereon. Once a die bond pad configuration is known, the test membrane can be configured for the die bond pads by using a laser under software control to define connection pads correlating to the die bond pads and also to define interconnecting conductive traces from the connecting pads to contact pads that can be connected to test equipment. In one embodiment, the laser operates to ablate a continuous conductive coating, so as to form conductive pads and traces. In another embodiment, the laser is used to cut various lines in a matrix of conductive lines, so as to define conductive paths from the bond pads to the contact pads for connection to the test equipment.

US Patent:

6636063, Oct 21, 2003

Filed:

Oct 2, 2001

Appl. No.:

09/968963

Inventors:

Richard W. Arnold - McKinney TX
James Forster - Barrington RI
Reynaldo M. Rincon - Richardson TX
Lester Wilson - Sherman TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G01R 3102

US Classification:

324762, 3241581

Abstract:

A probe card having reliable âmicro probeâ contacts which include a base and an angled probe tip fabricated as a single unit from a thin sheet of a conductive metal having high tensile and yield strength, and coated with a noble metal. The micro probes are secured into precisely dimensioned, and positioned locations on the card, and are electrically connected to traces on the card. Design of the micro probes includes not only the base and probe tip, but also locking features, a stand-off to prevent over compression, and a necked down stem feature for release from the support strap used in transporting and plating during the manufacturing processes.

US Patent:

6720574, Apr 13, 2004

Filed:

Nov 8, 2001

Appl. No.:

09/986341

Inventors:

Richard W. Arnold - McKinney TX
Weldon Beardain - Denison TX
Daniel W. Prevedel - Fort Collins CO
Donald E. Riley - Midland TX
Lester L. Wilson - Sherman TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2358

US Classification:

257 48, 438 14, 438 15, 438 16, 438 17, 438 18

Abstract:

An apparatus for testing a semiconductor die and the method wherein there is provided a package having a cavity therein with a plurality of terminals in the package disposed at the periphery of the cavity. A semiconductor die to be tested and having a plurality of bond pads thereon is disposed in the cavity and an interconnecting layer having electrically conductive paths thereon is also disposed in the cavity, each of the paths having first and second spaced apart regions thereon, the first region of each path being aligned with and contacting a bond pad. An interconnection is provided between the second spaced apart region of each of the paths and one of the plurality of terminals. The second spaced apart region of each of the paths is preferably a bump aligned with and contacting one of the plurality of terminals. A compliant layer is preferably disposed over the interconnecting layer and provides a force causing engagement of at least the first spaced apart regions and the bond pads. The first region is preferably a compliant bump probe tip having a first predetermined height above the layer and includes a standoff on the layer having a second predetermined height above the layer less than the first height.

US Patent:

6720780, Apr 13, 2004

Filed:

Aug 2, 2001

Appl. No.:

09/921169

Inventors:

Reynaldo M. Rincon - Richardson TX
Jerry Broz - Longmont CO
Lester Wilson - Sherman TX
Richard W. Arnold - McKinney TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G01R 3102

US Classification:

324754

Abstract:

A high density probe card contact apparatus including a support block fitted into an opening in a probe card, and holding a plurality of fine tipped needles extending inward and below an opening in the center of the block. The needle tips are a noble metal integrally connected with a less costly conductive metal which forms the more widely spaced fingers of the needles, and which terminate in contacts to the probe card. Laser etching defines the fine needle pattern in a thin sheet of the two-metal composition which is secured to a polymeric film. The contact apparatus is assembled by positioning one or more sections of the polymer with needles on the support film.

US Patent:

7122895, Oct 17, 2006

Filed:

May 1, 2001

Appl. No.:

09/845344

Inventors:

Richard W. Arnold - McKinney TX, US
Weldon Beardain - Denison TX, US
Lester L. Wilson - Sherman TX, US
James A. Forster - Barrington RI, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 23/52
H01L 23/48

US Classification:

257738, 257778, 257E2306

Abstract:

A method of forming a membrane for use in conjunction with a semiconductor carrier and the membrane which includes an electrically insulating substrate and an interconnect pattern formed on the substrate. A stud is coupled to the interconnect pattern over the substrate by forming a gold ball, preferably by gold ball bonding techniques, and coating a portion of the gold ball with a compliant material, preferably an epoxy resin. The coating is filled with a material having sufficient hardness to be capable of penetrating the oxide film on the contact pads of semiconductor devices. The flakes are preferably silver or silver-based.