Li Li

US Patent:

6352192, Mar 5, 2002

Filed:

Feb 29, 2000

Appl. No.:

09/515185

Inventors:

Tien-Yu Tom Lee - Phoenix AZ
James Vernon Hause - Maricopa AZ
Li Li - Gilbert AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

B23K 1005

US Classification:

228102, 228105, 2282621, 2281801

Abstract:

A system ( ) and method are used for predicting and controlling the temperature of a semiconductor wafer ( ) during a solder reflow process by controlling the operating profile of a solder reflow furnace ( ). The emissivity of the surface of the wafer ( ) is measured using an infrared device ( ) prior to the solder reflow process. Using the measured emissivity value of the wafer ( ), the peak temperature of the wafer ( ) is predicted, and the operating profile of the solder reflow furnace ( ) is adjusted accordingly to achieve a desired temperature profile of the wafer ( ). A process for reflowing solder on a semiconductor wafer calculates a predicted peak temperature of a semiconductor wafer ( ) and controls the actual temperature of the wafer ( ) during a solder reflow process by controlling the operating profile of a solder reflow furnace ( ).

US Patent:

6451127, Sep 17, 2002

Filed:

Jun 1, 1999

Appl. No.:

09/323464

Inventors:

Li Li - Gilbert AZ
Treliant Fang - Chandler AZ

Assignee:

Motorola, Inc. - Schaumbrug IL

International Classification:

B23K 35363

US Classification:

148 23, 148 24

Abstract:

A conductive paste composition is described which comprises an alloy of tin and a flux composition. The flux composition comprises an aromatic carboxylic acid fluxing agent and a polymeric solvent.

US Patent:

6669079, Dec 30, 2003

Filed:

Aug 2, 2002

Appl. No.:

10/211631

Inventors:

Li Li - Gilbert AZ
Treliant Fang - Chandler AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

B23K 3526

US Classification:

2282629, 148 23, 148 24

Abstract:

A conductive paste ( ) for use in making conductive bumps ( ) and a method for using the conductive paste to make conductive bumps ( ) on a substrate ( ). The conductive paste ( ) is formed by combining a tin alloy with a flux composition containing an aromatic carboxylic acid fluxing agent and a solvent. The conductive paste ( ) is disposed on underbump metallization layers ( ) and reflowed to form the conductive bumps ( ).

US Patent:

6841736, Jan 11, 2005

Filed:

Sep 26, 2002

Appl. No.:

10/256789

Inventors:

Li Li - Gilbert AZ, US

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01B 708

US Classification:

174117FF, 174117 R, 174117 AS

Abstract:

An embodiment of a current-carrying structure () includes a first electrically conductive layer () and a second electrically conductive layer (). The second electrically conductive layer is in contact with the first electrically conductive layer along substantially the entire length of the first electrically conductive layer. The second electrically conductive layer is above the first electrically conductive layer. A non-electrically conductive layer () is in contact with the first electrically conductive layer and the second electrically conductive layer. A current travels simultaneously through the first electrically conductive layer and the second electrically conductive layer.

US Patent:

7136274, Nov 14, 2006

Filed:

Oct 28, 2004

Appl. No.:

10/975720

Inventors:

Robert B. Lempkowski - Elk Grove IL, US
Li Li - Scottsdale AZ, US

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01G 4/228

US Classification:

3613063, 3613061, 3613211, 361767, 361794, 174 522, 174255, 174260

Abstract:

An embedded multilayer printed circuit includes a first ground plane () of a multilayer printed circuit board and an embedded layer. The embedded layer includes a co-planar capacitor (), a distributed inductor (), and a capacitive plate () circuit. The capacitive plate is a plate of a vertical capacitor (). The embedded layer further includes a node () of the embedded multilayer printed circuit that is formed by a connection of a first terminal of the co-planar capacitor and a first terminal of the first distributed inductor, and in some embodiments, the first capacitive plate is also connected to the node. A second terminal of one of the co-planar capacitor and the distributed inductor is connected to the first ground plane.

US Patent:

7446017, Nov 4, 2008

Filed:

May 31, 2006

Appl. No.:

11/444091

Inventors:

Lianjun Liu - Chandler AZ, US
Philip H. Bowles - Fountain Hills AZ, US
Li Li - Scottsdale AZ, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 21/30

US Classification:

438455, 438106, 438107, 438109, 257E21122, 257E21567

Abstract:

A patterned ground shield (PGS) () in a vertically-integrated structure includes a patterned conductor (e. g. , a metallic layer) provided between a first substrate () having a first semiconductor device ( formed therein and a second substrate () having a second device () formed therein. A bonding layer () is used to bond the vertically-integrated die and/or wafers. The PGS may be formed on a surface (e. g. , the backside) of the second (topmost) substrate, or may be formed over the first semiconductor device—for example, on a dielectric layer formed over the first semiconductor device. The PGS may consist of parallel stripes in various patterns, or may be spiral-shaped, lattice-shaped, or the like.

US Patent:

20080246126, Oct 9, 2008

Filed:

Apr 4, 2007

Appl. No.:

11/696374

Inventors:

Philip H. Bowles - Fountain Hills AZ, US
Li Li - Scottsdale AZ, US
Lianjun Liu - Chandler AZ, US

Assignee:

FREESCALE SEMICONDUCTOR, INC. - Austin TX

International Classification:

H01L 23/552
H01L 21/58

US Classification:

257659, 438109, 257E23114, 257E21505

Abstract:

According to an example embodiment, a stacked die package includes a first die (), first active circuitry () disposed on an upper surface of the first die, and a first conductive pattern () disposed on the first active circuitry. The stacked die package further includes a second die () disposed over the first die, where the first die is wider than the second die in a cross-section of the stacked die package, second active circuitry () disposed on an upper surface of the second die, and a second conductive pattern () disposed on the second active circuitry. The stacked die package further includes a first wirebond () that connects the first conductive pattern to the second conductive pattern and a mold compound () disposed on the first die, the mold compound encapsulating the second die and the wirebond.

US Patent:

20090171166, Jul 2, 2009

Filed:

Dec 22, 2008

Appl. No.:

12/340978

Inventors:

Scott Amundson - Boulder CO, US
Corydon A. Hinton - Oakland CA, US
Li Li - Milpitas CA, US

Assignee:

Nellcor Puritan Bennett LLC - Boulder CO

International Classification:

A61B 5/02
A61B 5/00

US Classification:

600301, 600424

Abstract:

According to embodiments, systems and methods are provided for determining the location of a medical device. A system may include a plurality of wireless communication devices configured to receive signals from a medical device and a location server configured to receive information from the plurality of wireless communication devices and determine the location of the device within a specified range. A method of operation may include receiving a plurality of signals corresponding to a medical device from a plurality of wireless communication devices and determining the location of the medical device from the plurality of signals. A sensor and monitor configured to transmit location information to one or more wireless communication devices are also provided.