Liang Wang

US Patent:

20190252375, Aug 15, 2019

Filed:

Feb 9, 2018

Appl. No.:

15/892734

Inventors:

- San Jose CA, US
David Edward FISCH - Pleasanton CA, US
Kenneth DUONG - San Jose CA, US
Xu CHANG - San Jose CA, US
Liang WANG - Milpitas CA, US

International Classification:

H01L 27/06
H01L 27/12
H01L 23/00
H03K 17/687

Abstract:

A microelectronic circuit structure comprises a stack of bonded layers comprising a bottom layer and at least one upper layer. At least one of the upper layers comprises an oxide layer having a back surface and a front surface closer to the bottom layer than the back surface, and a plurality of FD-SOI transistors built on the front surface. At least a first back gate line and a second back gate line extend separate from each other above the back surface for independently providing a first back gate bias to a first group of transistors and a second back gate bias to a second different group of transistors.