Lin Wang

US Patent:

7979681, Jul 12, 2011

Filed:

Nov 20, 2007

Appl. No.:

11/943190

Inventors:

Suresh K. Venkumahanti - Austin TX, US
Lucian Codrescu - Austin TX, US
Shankar Krithivasan - Austin TX, US
Jian Shen - Austin TX, US
Lin Wang - Austin TX, US

Assignee:

QUALCOMM Incorporated - San Diego CA

International Classification:

G06F 9/00

US Classification:

712225, 712223

Abstract:

In a particular embodiment, a method is disclosed that includes identifying a first block of bits within a result to be written to a destination register by an execution unit. The result includes a plurality of bits having the first block of bits and a second block of bits. The first block of bits has a value of zero. The method further includes providing an encoded bit value representing the first block of bits to a control register and selectively writing the second block of bits, but not the first block of bits, to the destination register. The destination register is sized to receive the first and second blocks of bits.

US Patent:

8145874, Mar 27, 2012

Filed:

Feb 26, 2008

Appl. No.:

12/037300

Inventors:

Suresh Venkumahanti - Austin TX, US
Lucian Codrescu - Austin TX, US
Lin Wang - Austin TX, US

Assignee:

QUALCOMM Incorporated - San Diego CA

International Classification:

G06F 12/10
G06F 9/34

US Classification:

711202, 711169, 711217, 711E12061, 712218

Abstract:

In an embodiment, a method is disclosed that includes, comparing, during a write back stage at an execution unit, a write identifier associated with a result to be written to a register file from execution of a first instruction to a read identifier associated with a second instruction at an execution pipeline within an interleaved multi-threaded (IMT) processor having multiple execution units. When the write identifier matches the read identifier, the method further includes storing the result at a local memory of the execution unit for use by the execution unit in the subsequent read stage.

US Patent:

20090070554, Mar 12, 2009

Filed:

Sep 12, 2007

Appl. No.:

11/853866

Inventors:

Lin Wang - Austin TX, US
Masud Kamal - Pflugerville TX, US
Paul Bassett - Austin TX, US
Suresh Venkumahanti - Austin TX, US
Jian Shen - Austin TX, US

Assignee:

QUALCOMM INCORPORATED - San Diego CA

International Classification:

G06F 9/40

US Classification:

712205, 712E09082

Abstract:

The present disclosure includes a multi-threaded processor that includes a first register file associated with a first thread and a second register file associated with a second thread. At least one hardware resource is shared by the first and second register files. In addition, the first thread may have a pipeline access position that is non-sequential to the second thread. A method of accessing a plurality of register files is also disclosed. The method includes reading data from a first register file while concurrently reading data from a second register file. The first register file is associated with a first instruction stream and the second register file is associated with a second instruction stream. The first instruction stream is sequential to the second instruction stream in an execution pipeline of a processor, and the first register file is in a non-adjacent location with respect to the second register file.

US Patent:

20090327674, Dec 31, 2009

Filed:

Jun 27, 2008

Appl. No.:

12/147893

Inventors:

Lucian Codrescu - Austin TX, US
Erich James Plondke - Austin TX, US
Lin Wang - Austin TX, US
Suresh K. Venkumahanti - Austin TX, US

Assignee:

QUALCOMM INCORPORATED - San Diego CA

International Classification:

G06F 9/30

US Classification:

712241, 712E09016

Abstract:

Loop control systems and methods are disclosed. In a particular embodiment, a hardware loop control logic circuit includes a detection unit to detect an end of loop indicator of a program loop. The hardware loop control logic circuit also includes a decrement unit to decrement a loop count and to decrement a predicate trigger counter. The hardware loop control logic circuit further includes a comparison unit to compare the predicate trigger counter to a reference to determine when to set a predicate value.

US Patent:

20120117327, May 10, 2012

Filed:

Nov 8, 2010

Appl. No.:

12/941105

Inventors:

Suresh K. Venkumahanti - Austin TX, US
Lucian Codrescu - Austin TX, US
Stephen R. Shannon - Austin TX, US
Lin Wang - Austin TX, US
Phillip M. Jones - Austin TX, US
Daisy T. Palal - Las Vegas NV, US
Jiajin Tu - Austin TX, US

Assignee:

QUALCOMM INCORPORATED - San Diego CA

International Classification:

G06F 12/08

US Classification:

711125, 711E12016

Abstract:

Each branch instruction having branch prediction support has branch prediction bits in architecture specified bit positions in the branch instruction. An instruction cache supports modifying the branch instructions with updated branch prediction bits that are dynamically determined when the branch instruction executes.

US Patent:

20190196867, Jun 27, 2019

Filed:

May 18, 2018

Appl. No.:

15/983992

Inventors:

- San Diego CA, US
Suresh Kumar Venkumahanti - Austin TX, US
Lin Wang - Pullman WA, US
Lucian Codrescu - Austin TX, US

International Classification:

G06F 9/48

Abstract:

A processor includes priority adjustment circuitry configured to adjust a priority of a thread of multiple threads configured to execute tasks to have a software-defined priority value or a designated high priority value. The processor also includes circuitry configured to identify a lowest priority thread of the multiple threads and a control unit configured to cause the lowest priority thread to take a pending interrupt.

US Patent:

20150324239, Nov 12, 2015

Filed:

May 7, 2014

Appl. No.:

14/271812

Inventors:

- San Diego CA, US
Stephen Robert Shannon - Austin TX, US
Lin Wang - Austin TX, US

Assignee:

QUALCOMM Incorporated - San Diego CA

International Classification:

G06F 9/50
G06F 9/30

Abstract:

Dynamic load balancing of hardware threads in clustered processor cores using shared hardware resources, and related circuits, methods, and computer readable media are disclosed. In one aspect, a dynamic load balancing circuit comprising a control unit is provided. The control unit is configured to determine whether a suboptimal load condition exists between a first cluster and a second cluster of a clustered processor core. If a suboptimal load condition exists, the control unit is further configured to transfer a content of private register(s) of a first hardware thread of the first cluster to private register(s) of a second hardware thread of the second cluster via shared hardware resources of the first hardware thread and the second hardware thread. The control unit is also configured to exchange a first identifier associated with the first hardware thread with a second identifier associated with the second hardware thread via the shared hardware resources.