Lin Mei Yuan

US Patent:

20100190277, Jul 29, 2010

Filed:

Jan 23, 2009

Appl. No.:

12/359091

Inventors:

Yan Lin - Sunnyvale CA, US
Yi-Min Jiang - San Jose CA, US
Lin Yuan - Mountain View CA, US

Assignee:

Synopsys, Inc. - Mountain View CA

International Classification:

H01L 21/66
G06F 17/50

US Classification:

438 17, 716 5, 257E21521

Abstract:

A method of automatically reducing stacked vias while minimizing voltage drop in a power network of an integrated circuit (IC) is provided. In this method, any feasible (i.e. other than connectivity-necessary and uncongested stacked vias) stacked vias of the power network can be virtually removed. If a target voltage drop of the power network is exceeded, then a measurement of the severity of at least a maximum voltage drop on the IC can be updated. After this updating, a set of voltage drop improvement stacked vias can be virtually returned to the power network. The steps of determining whether the target voltage drop is exceeded, updating the severity of the voltage drop at one or more hot spots, and virtually returning the set of additional stacked vias can be repeated until the target voltage drop is not exceeded.

US Patent:

20140189629, Jul 3, 2014

Filed:

Mar 22, 2013

Appl. No.:

13/849427

Inventors:

- Mountain View CA, US
Yi-Min Jiang - Mountain View CA, US
Phillip H. Tai - Mountain View CA, US
Lin Yuan - San Jose CA, US

Assignee:

Synopsys, Inc. - Mountain View CA

International Classification:

G06F 17/50

US Classification:

716127

Abstract:

Systems and techniques for pattern-based power-and-ground (PG) routing and via rule based via creation are described. A pattern for routing PG wires can be received. Next, an instantiation strategy may be received, wherein the instantiation strategy specifies an area of an integrated circuit (IC) design layout where PG wires based on the pattern are to be instantiated and specifies one or more net identifiers that are to be assigned to the instantiated PG wires. The PG wires can be instantiated in the IC design layout based on the pattern and the instantiation strategy. Additionally, a set of via rules can be received, wherein each via rule specifies a type of via that is to be instantiated at an intersection between two PG wires that are in two different metal layers. Next, one or more vias can be instantiated in the IC design layout based on the set of via rules.