Lin Zheng

US Patent:

20130091392, Apr 11, 2013

Filed:

Dec 30, 2011

Appl. No.:

13/341614

Inventors:

Magesh VALLIAPPAN - Austin TX, US
Lin Zheng - Newark CA, US
Bruce Howard Conway - Aliso Viejo CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

G06F 11/07

US Classification:

714700, 714E11024

Abstract:

A method and a system for accurately calculating the timing margin in a clock and data recovery system (CDR) is provided that utilizes a singular path environment of hardware. The method entails adding an amount of jitter within the CDR to change the receiver phase. The amount of jitter is incrementally increased until a threshold level of bit errors occur. Based on the amount of jitter needed to cause the threshold level of bit errors, timing margin can be calculated.